| Last change
 on this file since 643 was             637, checked in by ansari, 26 years ago | 
        
          | 
archediab version 24 initial import
 | 
        
          | File size:
            1.3 KB | 
      
      
| Rev | Line |  | 
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| [637] | 1 |  | 
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|  | 2 | //      ________________________________________  adresses nubus  (adresses pci dans pci.h)  ________________________ | 
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|  | 3 |  | 
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|  | 4 | //#if defined( _avec_PCI)       //      ________________________________________  carte PCI  ________________________ | 
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|  | 5 |  | 
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|  | 6 | #define lit_carte               RR=*fifo_p | 
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|  | 7 | #define ecrit_carte(x)          (*fifo_p=(unsigned long ) x) | 
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|  | 8 | #define reset_carte             {*reset_p=0L;while(*fifo_p) controlemanip(0);} | 
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|  | 9 |  | 
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|  | 10 | /* | 
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|  | 11 | #else   //      ________________________________________________________  sans interface  ________________________ | 
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|  | 12 |  | 
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|  | 13 |  | 
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|  | 14 | #define lit_carte               {RR=FLAG_NFIFOHF;}                      // les trois bit controle nubus=3 -> qqchose à lire | 
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|  | 15 | #define ecrit_carte(x)          {} | 
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|  | 16 | #define reset_carte             {} | 
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|  | 17 |  | 
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|  | 18 | #endif | 
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|  | 19 | */ | 
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|  | 20 | //__________________________________________________________________________________________ | 
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|  | 21 | //------------------------ decodage apres lecture carte d'interface  ----------------------- | 
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|  | 22 | //__________________________________________________________________________________________ | 
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|  | 23 |  | 
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|  | 24 |  | 
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|  | 25 | //      ________________________________________  carte PCI  ou  rien  ______________________ | 
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|  | 26 |  | 
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|  | 27 |  | 
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|  | 28 | #define rien_a_lire  (!RR) | 
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|  | 29 | #define octet_a_lire  (RR & 0xff) | 
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|  | 30 |  | 
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|  | 31 | #define fifo(x)         ((RR>>(x))&1) | 
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|  | 32 | #define fifo0           (RR & 0x1L)             //  tire 1 bit (fifo0) (ligne retour cout à 1 1 coups sur 16 + 2 coups à chaque debut de periode ) | 
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|  | 33 | #define fifo12          (RR & 0x1000L)          //  tire 1 bit (fifo12) | 
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|  | 34 | #define fifo13          (RR & 0x2000L)          //  tire 1 bit (fifo13) | 
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|  | 35 |  | 
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|  | 36 |  | 
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|  | 37 |  | 
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