| 4 | | == Status about the interlock development for the XFEL (2008.02.25) (sk, cm, goe) == |
| 5 | | |
| 6 | | === . === |
| 7 | | At FLASH we are using successfully a interlock system, which needed to be improved accordingly the special needs in the XFEL linac. (Like full remote controll.) |
| 8 | | |
| 9 | | === . === |
| 10 | | |
| 11 | | Therefore we first build up, the so called MI or AMTF Interlock. This permitts already most of the needed functionality, except that the fast ADCs needs to be connected externaly (delivered from the control system). Some features: |
| 12 | | * full remote controlled. |
| 13 | | * hard wired interlock electronic (analog comparators, the logic is realized in a CPLD without additional clock). |
| 14 | | * remote controlled sensor interfaces, including a test function for supported sensors. |
| 15 | | |
| 16 | | The first prototype is running fine. |
| 17 | | |
| 18 | | The production of the pre-series is ongoing. |
| 19 | | |
| 20 | | Next Steps: |
| 21 | | |
| 22 | | * Programming of the DOOCS server. |
| 23 | | * Development of a new light sensor with test functionality. |
| 24 | | |
| 25 | | === The interlock for the XFEL === |
| 26 | | |
| 27 | | The interlock for the XFEL should be improved in the following manner: |
| 28 | | * Higher channel density (if possible) |
| 29 | | * Fast ADCs can be combined with the interlock logic on FPGAs. |
| 30 | | |
| 31 | | Status about the XFEL-IL: |
| 32 | | |
| 33 | | * The AMC board (xTCA) is ordered and will be expected in May 2008. The interlock logic (incl. digital comparators) will be realized by the onboard FPGA, which is full involved in the controlsystem, too. |
| 34 | | * The pickypacks will contain the fast ADCs (a copy from the controlsystem mainstream) and the sensor interfaces (which are copied from the pickypacks of the MI/AMTF interlock). A pickypack for tests of the FPGA (2ADCs) is in production. The circuit and layout of the interlock pickypack will be ready soon. |
| 35 | | |
| 36 | | Next: |
| 37 | | * Programming of the FPGA for interlock purpose. |
| 38 | | * Programming of the DOOCS servers to control the interlock. |
| 39 | | |
| 40 | | === connectors === |
| 41 | | |
| 42 | | Most of the connectors for the external cabling are defined. |
| 43 | | |
| 44 | | === . === |
| 45 | | The prototype of the special electronic for the e- detection via the Ubias (on the inner conductor of the RF coupler) will be tested soon. (Developed by Anton Labanc) |
