Changeset 473 for Selma/PARISROC/parisroc-jinst.tex

Timestamp:

Sep 8, 2009, 12:34:54 PM (15 years ago)

Author:

campagne

Message:

Version from Word doc (JEC)

File:

• Selma/PARISROC/parisroc-jinst.tex (modified) (5 diffs)

Selma/PARISROC/parisroc-jinst.tex

@@ -1 +1 @@
 \documentclass{JINST}
-%\usepackage{graphicx}
 \usepackage[pdftex]{graphicx}
 \usepackage[figuresright]{rotating}
-\usepackage[T1]{fontenc}
+%\usepackage{graphicx}
+%\usepackage[T1]{fontenc}
 \usepackage{eurosym}
-\usepackage{rotating}
+%\usepackage{rotating}
+%\usepackage[dvips]{color}
+
 
 %used explicitly in the text
@@ -15 +17 @@
 
 
-\title{Large underground, liquid based detectors for astro-particle physics in Europe: scientific case and prospects}
+\title{PARISROC, a Photomultiplier Array Integrated Readout Chip.}
 %
 
-\author{First Author$^a$, Second Author$^b$\thanks{Corresponding
+\author{S. Conforti$^a$, Second Author$^b$\thanks{Corresponding
 author.}~ and Third Author$^b$\\
-\llap{$^a$}Name of Institute,\\
-  Address, Country\\
+\llap{$^a$}Laboratoire de l'Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud 11,
+Bât. 200, 91898 Orsay Cedex, France\\
 \llap{$^b$}Name of Institute,\\
   Address, Country\\
-  E-mail: \email{CorrespondingAuthor@email.com}}
+  E-mail: \email{conforti@lal.in2p3.fr}}
 
 
@@ -30 +32 @@
 
 \abstract{
-
-This document reports on a series of experimental and theoretical studies conducted to 
-assess the astro-particle physics potential of three future large-scale particle detectors 
-proposed in Europe as next generation underground observatories. 
-
+PARISROC is a complete read
+out chip, in AMS SiGe 0.35 \begin{math}\mu{}\end{math}m technology
+\cite{ref1}
+%[1]
+, for photomultipliers array. It allows triggerless acquisition for
+next generation neutrino experiments and it belongs to an R\&D program
+funded by French national agency for research (ANR) called
+PMm2: "`Innovative electronics for photodetectors array
+used in High Energy Physics and Astroparticles"'
+\cite{ref2}
+%[2]
+(ref.ANR-06-BLAN-0186). The ASIC integrates 16 independent and auto
+triggered channels with variable gain and provides charge and time
+measurement by a 12-bit ADC and a 24-bit Counter. The charge
+measurement should be performed from 1 up to 300 pe with a good
+linearity. The time measurement allowed to a coarse time with a 24-bit
+counter at 10 MHz and a fine time on a 100ns ramp to achieve a
+resolution of 1 ns. The ASIC sends out only the relevant data through
+network cables to the central data storage.
 }%end of abstract
 
@@ -40 +56 @@
 %97.60.Bw}
 
-%\submitto{Journal of Cosmology and Astroparticle Physics}
+%\submitto{Journal of Instrumentation}
 
 \keywords{Keyword1; Keyword2; Keyword3}
@@ -48 +64 @@
 \bibliographystyle{Campagne}
 
-\section{Physics motivation}
-\label{sec:Phys-Intro}
-
-Our last citation \cite{Genolini:2008uc}.....
-
-The RMS error is $\sigma$...
-
-
-Several outstanding physics goals could be achieved by the next generation of large underground observatories
-in the domain of astro-particle and particle physics, neutrino astronomy and cosmology.
-Proton decay \cite{Pati:1973rp}, in particular, is one of the most exciting prediction of Grand Unified Theories 
-(for a review see \cite{Nath:2006ut}) aiming at the 
-unification of fundamental forces in Nature. It remains today one of the most relevant open questions
-of particle physics. Its discovery would certainly represent a fundamental milestone, contributing to clarifying our
-understanding of the past and future evolution of the Universe.  
-
+\section{Introduction}
+\label{sec:Intro}
+
+The PMm2 project: "`Innovative electronics for
+photodetectors array used in High Energy Physics and
+Astroparticles"' \cite{ref2}
+%[2]
+proposes to segment the large surface of photodetection in macro
+pixel consisting of an array of 16 photomultipliers connected to an
+autonomous front-end electronics () and powered by a common High
+Voltage. These large detectors are used in next generation proton decay
+and neutrino experiment (i.e. the post-SuperKamiokande detectors as
+those that will take place in megaton size water tanks) and will
+require very large surfaces of photo detection and a large volume of
+data. The micro-electronics group's (OMEGA from the LAL at Orsay)
+purpose is the front-end electronics conception and
+realization. This R\&D \cite{ref2}
+%[2]
+involves three French laboratories (LAL Orsay, LAPP Annecy, IPN
+Orsay) and ULB Bruxells for the DAQ. It is funded for three years by
+the French National Agency for Research (ANR) under the reference
+ANR-06-BLAN-0186.
+
+
+LAL Orsay is in charge of the design and tests of the readout chip
+named PARISROC which stands for Photomultiplier ARrray Integrated in
+Si-Ge Read Out Chip.
 
 \begin{figure}[htb]
 \begin{center}
-    \includegraphics[scale=0.5]{./test_figs/varvscycle.pdf}
+\includegraphics[width=0.7\columnwidth]{img0.jpg}
+\caption{Principal of PMm2 proposal for megaton scale Cerenkov water
+tank.}
+\label{fig:1}
 \end{center}
-\caption{Example of figure PDF}
-\label{fig:1}
-\end{figure}          
-
-
-
-
+\end{figure}
+
+The detectors such as SuperKamiokande, are large tanks covered by a
+significant number of large photomultipliers (20"),
+the next generation neutrino experiments will require a bigger surface
+of photo detection and thus more photomultipliers. As a consequence the
+total cost has an important relief \cite{ref1}.
+\begin{itemize}
+        \item A smaller number of electronics, thanks to the 16 PMTs macropixel with
+a common electronics, even if it induces more electronic channels;
+        \item A common High Voltage for the 16 PMTs so a reduced number of
+underwater cables, cables  that are also used to brought the DATA to
+the surface;
+        \item The front-end closed to the PMTs that allow a suppression of
+underwater connector.
+\end{itemize}
+
+The general principle of PMm2 project is that the ASIC and a FPGA
+manage the dialog between the PMTs and the surface controller (\refFig{fig:2}).
+
+\begin{center}
 \begin{figure}[htb]
+%%\includegraphics[width=0.7\columnwidth]{img1.eps}
+\caption{Principle of the PMm2 project.}
+\label{fig:2}
+\end{figure}
+\end{center}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{PARISROC architecture}
+\label{sec:PARISROCArchi}
+The ASIC Parisroc is composed of 16 analogue channels managed by a
+common digital part (\refFig{fig:3}).
+
 \begin{center}
-    \includegraphics[scale=0.5]{./test_figs/pulse_snapshot.jpg}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img2.eps}
+\caption{PARISROC global schematic.}
+\label{fig:3}
+\end{figure}
 \end{center}
-\caption{Example figure JPEG}
-\label{fig:2}
-\end{figure}         
-
-Several experiments have been built and conducted to search for proton decay but they only yielded lower limits to the proton lifetime. 
-The window between the predicted proton lifetime (in the simplest models typically below $10^{37} $ years) and that excluded 
- by experiments \cite{Kobayashi:2005pe}
-($O$($10^{33}$) years, depending on the channel) is within reach, 
-and the demand to fill the gap grows with the progress in other domains of particle physics, astro-particle physics and cosmology. 
-To some extent, also a negative result from next generation high-sensitivity experiments
-would be relevant to rule-out some of the
-theoretical models based on SU(5) and SO(10) gauge symmetry or to further constrain the range of allowed parameters.
-Identifying unambiguously proton decay and measuring its lifetime would set a firm scale for any Unified Theory, narrowing
-the phase space for possible models and their parameters. This will be a mandatory step to go forward 
-beyond the Standard Model of elementary particles and interactions.
-
-Another important physics subject is the physics of 
-%natural (A. Mirizzi 15may07)
-astrophysical
-neutrinos, as those from supernovae, from the Sun and from the interaction of primary cosmic-rays with the Earth's atmosphere. Neutrinos are above all important messengers from stars. 
-Neutrino astronomy has a glorious although recent history, from the detection of solar neutrinos 
- \cite{Davis:1968cp,Hirata:1989zj,Anselmann:1992um,Abdurashitov:1994bc,Smy:2002rz,Aharmim:2005gt,Altmann:2005ix} 
-to the observation of neutrinos from supernova explosion, \cite{Hirata:1987hu,Bionta:1987qt,Alekseev:1988gp},
-acknowledged by the Nobel Prizes awarded to M. Koshiba and R. Davis.
-These observations have given valuable information for a better understanding of the functioning
-of stars and of the properties of neutrinos. However, much more information could be obtained if the energy spectra of
-stellar neutrinos were known with higher accuracy.
-Specific neutrino observations could give detailed information on the conditions of the production zone, 
-whether in the Sun or in a supernova. 
-A supernova explosion in our galaxy would be extremely important as the evolution mechanism of the collapsed star 
-is still a puzzle for astrophysics.
-An even more fascinating challenge would be observing neutrinos from extragalactic supernovae, either from identified sources 
-or from a diffuse flux due to unidentified past supernova explosions.
-
-Observing neutrinos produced in the atmosphere as cosmic-ray secondaries
-\cite{Aglietta:1988be,Hirata:1988uy,Hirata:1992ku,Becker-Szendy:1992hq,Daum:1994bf,Allison:1999ms,Ashie:2005ik} 
-gave the first compelling evidence
-for neutrino oscillation \cite{Fukuda:1998mi,Kajita:2006cy}, a process that unambiguously points to the existence of new physics. 
-While today the puzzle of missing atmospheric neutrinos can be considered solved, 
-there remain challenges related to the sub-dominant oscillation phenomena. In particular, precise measurements of
-atmospheric neutrinos with high statistics and small systematic errors \cite{TabarellideFatis:2002ni}
-would help in resolving ambiguities and degeneracies that hamper the interpretation 
-of other experiments, as those planned for future long baseline neutrino oscillation measurements.
-
-Another example of outstanding open questions is that of the knowledge of the interior of the Earth.  
-It may look hard to believe, but we know much better what happens inside the Sun than inside our own planet. 
-There are very few messengers that can provide information, while a mere theory is not sufficient for building a credible model for the Earth. However, there is a new unexploited window to the Earth's interior,
-by observing neutrinos produced in the radioactive decays of heavy elements in the matter. Until now, only the KamLAND 
-experiment  \cite{Araki:2005qa} has been able to study these so-called geo-neutrinos opening the way to a completely new
-field of research.  The small event rate, however,  does not allow to draw significant conclusions. 
-
-The fascinating physics phenomena outlined above, in addition to other important subjects that we will address in the following,
-could be investigated by a new generation of multipurpose 
-experiments based on improved detection techniques. 
-The envisioned detectors must necessarily be very massive (and consequently large) 
-due to the smallness of the cross-sections and to the low rate of signal events,
-and able to provide very low experimental background. 
-The required signal to noise ratio can only be achieved in underground laboratories suitably shielded against cosmic-rays
-and environmental radioactivity.
-We can identify three different and, to large extent, complementary technologies capable to meet the challenge, based
-on large scale use of liquids for building large-size, volume-instrumented detectors
-
-\begin{itemize}
-\item Water Cherenkov.
-As the cheapest available (active) target material, water is the only liquid that is realistic for extremely large detectors, 
-up to several hundreds or thousands of ktons;  detectors have sufficiently good resolution in energy, 
-position and angle. The technology is well proven, as previously used for the IMB, Kamiokande and Super-Kamiokande
-experiments.
-
-\item Liquid scintillator.
-Experiments using a liquid scintillator as active target
-provide high-energy resolution and offer low-energy threshold.  They are
-particularly attractive for low energy particle detection, as for example solar
-neutrinos and geo-neutrinos.  Also liquid scintillator detectors feature a well established technology, 
-already successfully applied at relatively large scale to the Borexino
-\cite{Back:2004zn} and KamLAND \cite{Araki:2004mb} experiments. 
-
-
-\item Liquid Argon Time Projection Chambers (LAr TPC).
-This detection technology has among the three the best performance in identifying the topology of
-interactions and decays of particles, thanks to the bubble-chamber-like imaging performance. 
-Liquid Argon TPCs are very versatile and work well with a wide particle energy range.
-Experience on such detectors has been gained within the ICARUS project \cite{Amerio:2004ze,Arneodo:2001tx}.
-\end{itemize}
-
-Three experiments are proposed to employ the above detection techniques: MEMPHYS \cite{deBellefon:2006vq} for WC,
-LENA \cite{Oberauer:2005kw, Marrodan:2006} for liquid scintillator 
-and GLACIER \cite{Rubbia:2004tz,Rubbia:2004yq,Ereditato:2004ru,Ereditato:2005ru,Ereditato:2005yx} for Liquid Argon. 
-In this paper we report on the study of the physics potential of the experiments and identify features of complementarity 
-amongst the three techniques. 
-
-Needless to say, the availability of future neutrino beams from particle accelerators 
-would provide an additional bonus to the above experiments.
-Measuring oscillations with artificial neutrinos (of well known kinematical features)
-with a sufficiently long baseline would allow to accurately determine the oscillation parameters
-(in particular the mixing angle $\theta_{13}$ and the possible
-CP violating phase in the mixing matrix). 
-The envisaged detectors may then be used for observing neutrinos from the future Beta Beams and Super Beams
-in the optimal energy range for each experiment. A common example 
-%C Volpe 19/10/07 is a low-energy Beta Beam from CERN to MEMPHYS at Frejus, 130 km away 
-is a Beta Beam from CERN to MEMPHYS at Frejus, 130 km away \cite{Campagne:2006yx}. 
-High energy beams have been suggested \cite{Rubbia:2006pi}, 
-favoring longer baselines of up to $O$(2000~km). 
-%add C. Volpe review
-An exhaustive review on the different Beta Beam scenario can be found in the reference \cite{Volpe:2006in}. 
-The ultimate Neutrino Factory facility will require a magnetized detector to fully exploit the simultaneous availability of 
-neutrinos and antineutrinos. This subject is however beyond the scope of the present study.
-
-Finally, there is a possibility of (and the hope for) unexpected
-discoveries. The history of physics has shown that 
-several experiments have made their glory with discoveries in research fields that were outside the original goals of the experiments. 
-Just to quote an example, we can mention the Kamiokande detector, mainly designed to search for proton decay
-and actually contributing to the observation of atmospheric neutrino oscillations, to the clarification of the solar neutrino puzzle and 
-to the first observation of supernova neutrinos \cite{Hirata:1987hu,Hirata:1988ad,Hirata:1989zj,Hirata:1988uy,
-Fukuda:1998mi}.
-All the three proposed experiments, thanks to their
-outstanding boost in mass and performance, will certainly provide a significant potential for surprises and unexpected discoveries.
-
-%
+
+Each analogue channel is made of a low noise preamplifier with
+variable and adjustable gain. The variable gain is common for all
+channels and it can change from 8 to 1 on 4 bits. The gain is also
+tuneable channel by channel to adjust the input detector's gain, up to
+a factor 4 to an accuracy of 7\% with 8 bits.
+
+The preamplifier is followed by a slow channel for the charge
+measurement in parallel with a fast channel for the trigger output.
+
+The slow channel is made by a slow shaper followed by an analogue
+memory with a depth of 2 to provide a linear charge measurement up to
+50~pC; this charge is converted by a 12-bits Wilkinson ADC. One follower
+OTA is added to deliver an analogue multiplexed charge measurement.
+
+The fast channel consists in a fast shaper (15~ns) followed by 2 low
+offset discriminators to auto-trig down to 50~fC. The thresholds are
+loaded by 2 internal 10-bit DACs common for the 16 channels and an
+individual 4bit DAC for one discriminator. The 2 discriminator outputs
+are multiplexed to provide only 16 trigger outputs. Each output trigger
+is latched to hold the state of the response until the end of the clock
+cycle. It is also delayed to open the hold switch at the maximum of the
+slow shaper. An "`OR"' of the 16 trigger gives a 17th output.
+
+
+For each channel, a fine time measurement is made by an analogue
+memory with depth of 2 which samples a 12-bit ramp, common for all
+channels, at the same time of the charge. This time is then converted
+by a 12 bit Wilkinson ADC.
+
+The two ADC discriminators have a common ramp, of 8/10/12 bits, as
+threshold to convert the charge and the fine time. In addition a bandgap bloc provides all voltage references.
+
+\begin{center}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img3.eps}
+\caption{PARISROC Layout.}
+\label{fig:4}
+\end{figure}
+\end{center}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Analogue Channel description and simulations}
+\label{ssec:AnalogChannel}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\refFig{fig:5} represents, in a schematic way, the detail of one channel analogue
+part.
+
+\begin{center}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img4.eps}
+\caption{PARISROC one channel analogue part schematic.}
+\label{fig:5}
+\end{figure}
+\end{center}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Preamplifier}
+\label{ssec:Preamplifier}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The input preamplifier is a low noise preamplifier with variable gain
+thanks to the switched input ($C_{in}$) and feedback ($C_f$) capacitors that
+can be adjusted (\refFig{fig:6}).
+
+This gain can vary changing $C_{in}$, which is
+common to the 16 channels, over 4 bits and $C_{f}$, to adjust preamplifier
+gain channel by channel. This adjustment allows correction of the PMT
+gain dispersion due to a use of a common HV.
+
+\begin{center}
+\begin{figure}[htb]
+        %%\includegraphics[width=0.7\columnwidth]{img5.eps}
+        \caption{PARISROC preamplifier schematic.}
+        \label{fig:6}
+\end{figure}
+\end{center}
+
+The preamplifier is designed as a voltage
+preamplifier in p-type Cascode structure to allow the acquisition of a
+fast input signal with a large dynamic range.
+
+The input transistor is a PMOS in common source
+configuration: $W = 800~\mu$m; $L = 0.35~\mu$m; the big input transistor is
+chosen to keep the preamplifier noise contribution low and to achieve a
+high gm. It supplies the output (the drain terminal) to the input
+terminal (source terminal) of the second stage transistor: $W = 100~\mu$m;
+$L = 0.35~\mu$m; the output transistor must be small to reach preamplifier
+high speed performances. The utility of the cascode preamplifier is in
+the large input impedance of the common source (with also the
+characteristic of Current Buffer) and better frequency response of a
+common Gate. An output buffer stage is designed in order to adapt the
+output impedance to the loaded impedance. The input dc level is high
+(about 2.6~V) while the output dc level is low (about 1~V). Because of
+the single side structure of preamplifier, it is hard to use the
+external reference voltage to set the dc operating point; the idea is
+to use an OTA as the dc feedback amplifier.
+
+In  \refFig{fig:7} are shown preamplifier's output waveforms
+for fixed gain and different input signal (left panel) and for fixed
+input signal and different preamplifier gain (right panel).
+
+\begin{center}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img6.eps}%%\includegraphics[width=0.7\columnwidth]{img7.eps}
+\caption{Simulated preamplifier output waveforms for different input
+signals with fixed gain (left panel) and for fixed input
+signal at different gain (different input capacitor values (right
+panel).}
+\label{fig:7}
+\end{figure}
+\end{center}
+
+The input signal, used in simulation, is a triangle signal with 4.5~ns
+rise and fall time and 5~ns of duration as shown in \refFig{fig:8}. This current
+signal is sent to an external resistor (50~Ohms) and varies from 0 to 5~mA 
+in order to simulate a PMT charge from 0 to 50~pC which represents 0
+to 300 photo-electrons when the PM gain is $10^{6}$.
+
+\begin{center}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img8.eps}
+\caption{Simulation input signal.}
+\label{fig:8}
+\end{figure}
+\end{center}
+
+The \refFig{fig:9} displays the input dynamic range allowed to the preamplifier
+linearity performance. \refTab{tab:1} lists the residuals obtained for different
+gains and shows a good linearity (better than $\pm 1\%$).
+
+\begin{center}
+\begin{figure}[hbtp]
+%%\includegraphics[width=0.7\columnwidth]{img9.eps}
+\caption{Preamplifier linearity.}
+\label{fig:9}
+\end{figure}
+\end{center}
+
+
+\begin{table}
+\centering
+        \caption{TO BE COMPLETED}
+        \label{tab:1}
+\begin{tabular}{|c|c|c|c|}
+\hline
+$G_{pa}$ &  $V_{out-max}$ &  $Qi_{max}/n_{pe}$ & Residuals (\%) \\
+\hline
+ 8 & 1.394~V  & 40~pC/250~pe & -0.6 to 0.2 \\
+ 4 & 0.841~V  & 48~pC/300~pe & -0.1 to 0.3 \\
+ 2 & 0.417~V  & 48~pC/300~pe & -0.2 to 0.3 \\
+\hline
+\end{tabular}
+\end{table}
+
+
+ 
+The \refFig{fig:10} displays the preamplifier noise with an
+rms value of 13~fC and a Signal to Noise ratio of $\approx 12$. 
+\refTab{tab:2} summarizes the results obtained.
+
+\begin{center}
+\begin{figure}[hbtp]
+\%%includegraphics{img10.eps}
+\caption{Preamplifier noise simulation; $G_{pa}=8$; $C_{in}=4$~pF and
+$C_{f}=0.5$~pF.}
+\end{figure}
+\label{fig:10}
+\end{center}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED}
+\label{tab:2}
+\begin{tabular}{|c|c|c|}
+\hline
+RMS  & SNR & $V_{out}(1 p.e)$  \\
+\hline
+$468~\mu$V ($\approx 1/12$~p.e, $\approx 13$~fC ) & 11.6 & 5.43~mV\\
+\hline
+\end{tabular}
+\end{table}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Trigger output}
+\label{ssec:Trigger}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The PARISROC is a self-triggered device. The fast channel has been
+conceived for this purpose.The amplified signal flows in a fast shaper that is a CRRC filter with
+a time constant of 15~ns. Its high gain allows to send high signal to
+the discriminator and thus to trigger easily on 1/3 of photo-electron.
+It has a classical design: differential pair is followed by a buffer.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img11.eps}
+\caption{Fast shaper schematics.}
+\label{fig:11}
+\end{figure}
+
+The \refFig{fig:12} represents the fast shaper output
+waveforms for a variable input signal. The \refTab{tab:3} lists the fast
+shaper principal characteristics obtained in simulation.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img12.eps}
+%%\includegraphics[width=0.7\columnwidth]{img13.eps}
+\caption{Simulated fast shaper outputs ($G_{pa} = 8$ with input from 1-10~pe (left panel)  
+and from 1/3~pe to 2~pe (right panel).}
+\label{fig:12}
+\end{figure}
+
+\begin{table}
+\centering
+        \caption{To be completed}
+        \label{tab:3}
+        \begin{tabular}{|c|c|c|c|}
+        \hline
+RMS  & SNR & $V_{out}(1 p.e)$  & $T_p$  \\
+\hline
+$2.36~\mu$V ($\approx 1/16$~p.e, $\approx 10$~fC ) & 16 & 37.85~mV & 8~ns\\
+        \hline
+        \end{tabular}
+\end{table}
+
+The fast shaper (15~ns) is followed by a low
+offset discriminator to auto-trig down to 50~fC (1/3~pe at $10^6$ gain). 
+
+
+The two discriminators can be used alone or
+simultaneously. Their outputs are multiplexed to ease the choice. Both
+are simple low offset comparators with the same schematic. The
+difference comes from the way to set the threshold. The first
+discriminator has the threshold sets by one 10-bit DAC, common to all
+16 channels, and one 4-bit DAC for each channel. The second
+discriminator has the threshold sets by only the 10 bit common DAC.
+Each output trigger is latched to hold the state of the response in SCA
+channel. In  \refFig{fig:13} are shown the triggers and the zoom of the triggers rise
+time in order to see the time walk of around 4~ns.
+
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img14.eps}
+%%\includegraphics[width=0.7\columnwidth]{img15.eps}
+\caption{Simulated trigger output (input charge from 0 to 10~p.e;
+threshold at 1/3~p.e). Zoom of trigger rise time on right
+pannel.}
+\label{fig:13}
+\end{figure}
+
+Each output trigger is latched to hold the
+state of the response in SCA channel.  SCA channel is the also called
+"`Analogue memory"'. The SCA has a
+depth equal to two; this means that there are two T\&H for time
+measurement as well as for charge measurement.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img16.eps}
+\caption{SCA (switched capacitor array) scheme.}
+\label{fig:14}
+\end{figure}
+
+The voltage level of the signal coming from
+slow shaper or ramp TDC cell is memorised in the T\&H capacitor (500~fF) 
+so "`Track \& Hold Cell"' allows
+to lock the capacitor value only when a calibrated trigger (from fast
+channel) occurs within the selected column. The SCA column is selected, read and erased by
+the digital part. 
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img17.eps}
+\caption{Operation of T\&H cell.}
+\label{fig:15}
+\end{figure}
+
+On  \refFig{fig:15} is illustrated the T\&H cell mode of
+operation: when a signal arrives in the discriminator cell is detected
+and the output trigger signal is sent to the T\&H cell.
+The output trigger is delayed and calibrated before being sent.
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Charge channel}
+\label{ssec:Charge}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The charge channel is the slow channel: the signal amplified by the
+variable gain preamplifier is sent to the slow shaper, a typical
+$\mathrm{CRRC}^2$ filter with variable peaking time. The
+peaking time can be set from 50~ns (default value) to 200~ns thanks to
+the switched feedback capacitors.
+
+On left part of \refFig{fig:16} are represented the slow shaper waveforms for
+different shaping times and the same input signal. The noise value (\refTab{tab:4}
+and right part of \refFig{fig:16}), from $980~\mu$V to $1.6$~mV (simulation results), foresee
+good noise performance.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img18.eps}
+%%\includegraphics[width=0.7\columnwidth]{img19.eps}
+\caption{Slow shaper output waveforms simulation (left panel). Slow shaper
+output noise simulation (right panel).}
+\label{fig:16}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED. $G_{pa} = 8$}
+\label{tab:4}
+\begin{tabular}{|c|c|c|c|}
+\hline
+Time constant & RMS  & SNR & $V_{out}(1 p.e)$ \\
+\hline
+50~ns & \parbox[t]{20mm}{$1.68$~mV \\ $\approx 1/17$~p.e \\ $ \approx 9$~fC}
+     &  11 
+                        & \parbox[t]{20mm}{$29$~mV \\ $T_p = 48$~ns } \\
+100~ns & \parbox[t]{20mm}{$1.26$~mV\\$\approx 1/12$~p.e \\ $ \approx 20$~fC}
+     &  8 
+                        & \parbox[t]{20mm}{$15$~mV \\ $T_p = 78$~ns }\\
+200~ns & \parbox[t]{20mm}{$0.98$~mV\\$\approx 1/5$~p.e \\ $ \approx 32$~fC}
+     &  5 
+                        & \parbox[t]{23mm}{$8$~mV \\ $ T_p = 141.5$~ns } \\
+\hline                  
+\end{tabular}
+\end{table}
+
+The \refFig{fig:17}  and \refTab{tab:5} illustrate the linearity performance for
+different time constants.  Simulations show a good linearity with
+residuals from -0.5\% to 0.2\% at $T_p = 50$~ns, from
+-1\% to 0.3\% at $T_p =100$~ns and -0.7\% to 0.3\% at
+$T_p=200$~ns.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth][width=273pt]{img20.eps}
+\caption{Slow shaper linearity simulation.}
+\label{fig:17}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED}
+\label{tab:5}
+\begin{tabular}{|c|c|c|c|}
+\hline
+Time constante & $V_{out-max}$ & $Qi_{max}/n_{pe}$ & Residuals (\%) \\
+\hline
+ 50~ns &  1.437~V &  13~pC/80~pe &  -0.5 to 0.2 \\
+100~ns &  1.493~V &  24~pC/150~pe &  -1.0 to 0.3 \\
+200~ns &  1.385~V &  48~pC/300~pe &  -0.7 to 0.3 \\
+\hline
+\end{tabular}
+\end{table}
+
+The Slow shaper maximum value, therefore the charge value, is then
+memorized in the analogue memory, with a depth of 2, thanks to the
+delayed trigger. \refFig{fig:18} gives the simulated slow shaper and SCA
+signals.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth][width=207pt]{img21.eps}
+\caption{Slow shaper \& SCA simulation.}
+\label{fig:18}
+\end{figure}
+This charge, stored as a voltage value, is then converted in digital
+value thanks to the 8/10/12 bit Wilkinson ADC.
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Time measurement}
+\label{ssec:Timemeas}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+For each channel, a fine time measurement is performed by the analogue
+memory with a depth of 2 which samples a 12 bit ramp (100~ns), common
+for all channels, at the same time of the charge.
+
+In \refFig{fig:19} is represented the TDC Ramp general schematic. The current,
+which flows in feedback, charges the capacitance $C_f$ when the switch is
+off. When the switch is turned off, $C_f$ discharges. Signals \verb|start\_ramp| and
+\verb|start\_ramp\_b| manage the switches. The rising signal starts the ramp
+and the falling signal stop the ramp (\refFig{fig:19}).
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img22.eps}
+%%\includegraphics[width=0.7\columnwidth]{img23.eps}
+\caption{TDC Ramp general schematic.}
+\label{fig:19}
+\end{figure}
+In order to avoid the large falling time of the ramp due to the $C_f$
+discharge time and the problem of non linearity at the start and the
+end of ramp signal (\refFig{fig:20}), the real ramp is created from two
+ramps.
+
+\begin{figure}[hbtp]
+\centering
+%%\includegraphics[width=0.7\columnwidth]{img24.eps}
+\caption{TDC Ramp.}
+\label{fig:20}
+\end{figure}
+
+The signal start ramp, coming from the digital
+part, enters in two delay cells. The two delayed signals create the
+first and second ramps. Commutating alternatively two switches the 100~ns ramp TDC is created 
+(\refFig{fig:21} and \refFig{fig:22}).
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics[width=0.7\columnwidth]{img25.eps}
+\caption{TDC Ramp scheme.}
+\label{fig:21}
+\end{figure}
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics[width=0.7\columnwidth]{img26.eps}
+\caption{TDC Ramp simulation.}
+\label{fig:22}
+\end{figure}
+
+This time value, stored as a voltage value, is then converted in
+digital value tanks to the 8/10/12 bit Wilkinson ADC.
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{ADC ramp}
+\label{ssec:ADCramp}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+In \refFig{fig:23} is represented the Ramp ADC general scheme. It is the
+same as TDC ramp one, the difference is in a variable current source
+which allows obtaining 8bit/10bit/12bit ADC according to the injected
+current. \refTab{tab:6} gives, for each ramp, the time duration to reach 3.3~V.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img27.eps}
+\caption{ADC ramp schematic.}
+\label{fig:23}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED}
+\label{tab:6}
+\begin{tabular}{|l|l|}
+\hline
+ Header 1      & Header 2 \\
+ 12 bit ADC & From 0.9~V to 3.3~V in $102.0~\mu{}$s \\
+ 10 bit ADC & From 0.9~V to 3.3~V in $25.6~\mu{}$s \\
+ \phantom{ }8 bit ADC & From 0.9~V to 3.3~V in $6.4~\mu{}$s \\
+\hline
+\end{tabular}
+\end{table}
+
+Then the ADC ramp is compared thanks to a Discriminator to the voltage
+values, which corresponds to charge and fine time values, stored in the
+SCA. The digital converted DATA are then treated by the digital part.
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Digital part}
+\label{ssec:Digital}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The digital part of PARISROC is built around 4 modules which are "`acquisition"', "`conversion"', "`readout"' and "`top manager"'. Actually, PARISROC is based on 2 memories. During acquisition,
+discriminated analog signals are stored into an analog memory (the SCA:
+switched capacitor array). The analog to digital conversion module
+converts analog charges and times from SCA into 12 bits digital values.
+These digital values are saved into registers (RAM). At the end of the
+cycle, the RAM is readout by an external system. The block diagram is
+given on \refFig{fig:24}.
+
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img28.eps}
+\caption{Block diagram of the digital part.}
+\label{fig:24}
+\end{figure}
+
+This sequence is made thanks to the top manager module which controls
+the 3 other ones. When 1 or more channels are hit, it starts ADC
+conversion and then the readout of digitized data. The maximum cycle
+length is about $200~\mu$s. During
+conversion and readout, acquisition is never stopped. It means that
+discriminated analog signals can be stored in the SCA at any time of
+the sequence shown in on \refFig{fig:25}.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img29.eps}
+\caption{Top manager sequence.}
+\label{fig:25}
+\end{figure}
+
+The first module in the sequence is the acquisition
+which is dedicated to charge and fine time measurements. It manages the
+SCA where charge and fine time are stored as a voltage like. It also
+integrates the coarse time measurement thanks to a 24-bit gray counter
+with a resolution of 100~ns. Each channel has a depth of 2 for the SCA
+and they are managed individually. Besides, SCA is treated like a FIFO
+memory: analog voltage can be written, read and erased from this
+memory.
+
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img30.eps}
+\caption{SCA analogue voltage}
+\label{fig:26}
+\end{figure}
+
+Then, the conversion module converts analog values stored in
+the SCA (charge and fine time: cf. \`refFig{fig:26}) in digital ones thanks to a 12-bit
+Wilkinson ADC. The counter clock frequency is 40~MHz, it implies a
+maximum ADC conversion time of $103~\mu$s
+when it overflows. This module makes 32 conversions in 1 run (16
+charges and 16 fine times).
+
+Finally, the readout module permits to empty all the registers
+to an external system. As it will only transfer hit channels, this
+module will tag each frame with its channel number: it works as a
+selective readout. The pattern used is composed of 4 data: 4-bit
+channel number, 24-bit coarse time, 12-bit charge and 12-bit fine time.
+The total length of one frame is 52 bits. The maximum readout time
+appears when all channels are hit. About 832 bits of data are
+transferred to the concentrator with a 10~MHz clock: the readout takes
+about $100~\mu$s with $1~\mu$s between 2 frames.
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{ASIC Laboratory tests}
+\label{sec:ASICLAbTest}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The PARISROC has been submitted in June 2008; a first batch of 6 ASICs
+has been produced and received in January 2009 (a second batch of 14
+ASICs in May 2009.
+
+The ASIC test has been a critical step in the PARISROC planning due to
+the ASIC complexity.A dedicated test board has been designed and realized for this purpose
+(\refFig{fig:27}). Its role is to allow the characterization of the chip and the
+communication between photomultipliers and ASIC. This is possible
+thanks to a dedicated Labview program that allows sending the ASIC
+configuration (slow control parameters; ASIC parameters, etc) and
+receiving the output bits via a USB cable connected to the test board.
+The Labview is developed by LAL.
+
+\begin{figure}[h]
+\centering
+%\includegraphics{img31.eps}
+\caption{Test Board.}
+\label{fig:27}
+\end{figure}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{General tests}
+\label{ssec:GeneralTest}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+On  \refFig{fig:28} is shown the Test Bench used in laboratory. It is composed by a
+test board, a signal generator, an oscilloscope, multimeters and PC to
+run labview program.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img32.eps}
+\caption{Test Bench.}
+\label{fig:28}
+\end{figure}
+
+The signal generator is a TEKTRONIX single
+channel function generator. It is used to create the input charge
+injected in the ASIC. The signal injected has the shaping as similar as
+possible to the PMT signal. On \refFig{fig:28} is represented the generator input
+signal and its characteristics.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img33.eps}
+%\includegraphics{img34.eps}
+\caption{Input signals}
+\label{fig:29}
+\end{figure}
+
+At the beginning all the standard electrical
+characteristics have been tested: DC levels, analogue output signals,
+the analogue part characteristics and then the pedestals, the DAC
+linearity, S\-curves (trigger efficiency as a function of the injected
+charge or the threshold), the ADC linearity. The first purpose is the
+comparison between simulation results and test measurements; most of
+them are in agreement with the ASIC characteristics, obtained in
+simulation.
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Analogue tests}
+\label{ssec:AnalogueTest}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The DC level characterization is the first step in ASIC
+characterization; in particular the DC uniformity of the analogue part
+DC level for the different channels has to be measured.
+
+In \refFig{fig:30} are represented the preamplifier, slow
+shaper and fast shaper DC uniformity plots. The DC uniformity test has a small dispersion
+of 0.4\%, 0.1\% and 0.05\% respectively for the preamplifier, the slow
+shaper and the fast shaper (\refTab{tab:7}).
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img35.eps}
+%\includegraphics{img36.eps}
+%\includegraphics{img37.eps}
+\caption{DC uniformity.}
+\label{fig:30}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED}
+\label{tab:7}
+\begin{tabular}{|l|c|c|c|}
+\hline
+DC level & RMS \\
+Preamplifier & 3.8~mV (0.40~\%) \\ 
+Slow shaper  & 1.3~mV (0.10~\%) \\
+Fast shaper  & 1.0~mV (0.05\%)  \\
+\hline
+\end{tabular}
+\end{table}
+
+The second step is the analogue part output signals: Injecting a
+charge equivalent to 10~pe, and setting a preamplifier gain at 8, are
+observed and compared with simulation results all the output waveforms.
+
+There is a good agreement in preamplifier results ( \refFig{fig:31} and \refTab{tab:8}), the
+amplitude has the same value while time rise value has a difference of
+3~ns. This difference is due to the output buffer placed in the test
+board.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img38.eps}
+%\includegraphics{img39.eps}
+\caption{Measurement and simulation of the preamplifier output for
+an input charge of 10~pe.}
+\label{fig:31}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED. Preamplifier parameters.... $G_{pa} = 8$. WHY not same parameters 1~pe and 10~p.e}
+\label{tab:8}
+\begin{tabular}{|l|c|c|}
+\hline
+             &  Measurement    & Simulation \\
+\hline
+Maximum voltage (10~pe) & 50.00~mV  & 50.83~mV \\
+Rise time (10~pe) & 7.78~ns & 4.79~ns \\
+RMS noise &       1~mV       & 0.47~mV \\
+without USB cable & 0.66~mV  &         \\
+Noise in pe   & 0.2  & 0.086 \\
+without USB cable & 0.132 &         \\
+Maximum voltage (1~pe) & 5.00~mV  & 5.43~mV \\
+SNR (1~pe ????) & 5 & 11.6 \\
+without USB cable & 7.5 &         \\
+\hline
+\end{tabular}
+\end{table}
+
+The slow shaper waveforms are shown in \refFig{fig:32} while \refTab{tab:9} 
+summarizes the results. The first differences appear: a different value
+in amplitude for slow shaper signal and fast shaper signal that is
+probably associate, also, to the Output Buffer. The second relevant
+difference is in noise value, in particular in slow shaper noise
+performance (\refTab{tab:9}).
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img40.eps}
+%\includegraphics{img41.eps}
+\caption{Measurement and simulation of the slow shaper output for an
+input charge of 10~pe.}
+\label{fig:32}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED. $G_{pa} = 8$ and $RC = 50$~ns.}
+\label{tab:9}
+\begin{tabular}{|l|c|c|}
+\hline
+             &  Measurement    & Simulation \\
+\hline
+Maximum Voltage (10~pe) & 117~mV & 290~mV \\
+Rise time (10~pe) & 18.0~ns & 19.1~ns \\
+RMS noise &  4.0~mV & 1.7~mV \\
+Noise in pe &  0.3 & 0.08 \\
+Maximum Voltage (1~pe) & 12~mV & 19~mV \\
+SNR &  3 & 11  \\
+\hline
+\end{tabular}
+\end{table}
+
+The Fast shaper results are shown in \refFig{fig:33}
+and \refTab{tab:10}.
+\begin{figure}[htb]
+        \centering
+%\includegraphics{img73.eps}
+%\includegraphics{img72.eps}
+        \caption{Measurement and simulation of the fast shaper output for an
+input charge of 1 pe.}
+        \label{fig:33}
+\end{figure}
+
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED. $G_{pa} = 8$.}
+\label{tab:10}
+\begin{tabular}{|l|c|c|}
+\hline
+             &  Measurement    & Simulation \\
+\hline
+RMS noise &  2.5~mV & 2.4~mV \\
+Noise in pe &  0.08 & 0.05 \\
+Maximum Voltage (1~pe) & 30~mV & 42~mV \\
+SNR &  12 & 18  \\
+\hline
+\end{tabular}
+\end{table}
+Another important characteristic is the
+linearity. The output voltage in function of the input injected charge
+is plotted for the different analogue signals. \refFig{fig:34} gives few examples for
+the preamplifier at different gains. \refTab{11} summarizes the fit
+results of these linearities. Good linearity performances are shown by
+residuals (better than $\pm 2~\%$) value but for a
+smaller dynamic range than simulation.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img42.eps}
+%\includegraphics{img43.eps}
+%\includegraphics{img44.eps}
+\caption{Preamplifier linearity for different gains.}
+\label{fig:34}
+\end{figure}
+
+\begin{table}
+\centering
+        \caption{TO BE COMPLETED}
+        \label{tab:11}
+\begin{tabular}{|c|c|c|c|}
+\hline
+Preamplifier Gains & Maximum voltage & Charge/Nb of pe & Residuals \\
+\hline
+8                  &   0.52~V        & 12~pC / 78~pe & -1.0~\% to 0.8~\% \\
+4                  &   0.64~V        & 32~pC / 198~pe & -1.0~\% to 1.0~\% \\
+2                  &   0.51~V        & 50~pC / 312~pe & -2.0~\% to 1.5~\% \\
+\hline
+\end{tabular}
+\end{table}
+
+
+\refFig{fig:35} represents an example of slow shaper
+linearity for a time constant of 50~ns and  a preamplifier gain of 8
+with residuals better than $pm 1~\%$.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img45.eps}
+\caption{Slow shaper linearity; $RC =50$~ns and $G_{pa}=8$.}
+\label{fig:35}
+\end{figure}
+
+\refFig{fig:36} gives an example of the fast shaper linearity until an injected
+charge of 10~pe. Residuals better than $ \pm 2~\%$
+are obtained.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img46.eps}
+\caption{Fast shaper linearity up to 10~pe.}
+\label{fig:36}
+\end{figure}
+
+The preamplifier linearity in function of
+variable feedback capacitor value with an input charge of 10~pe and
+with residuals from $-2.5~\%$ to $1.4~\%$ is represented on \refFig{fig:37} . The gain
+adjustment linearity is nice at 2~\% on 8 bits.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img47.eps}
+\caption{Preamplifier linearity vs feedback capacitor value.}
+\label{fig:37}
+\end{figure}
+
+On \refFig{fig:38}  is given the gain uniformity. For the
+different preamplifier gains is plotted the maximum voltage value for
+all channels in order to investigate the homogeneity among the whole
+chip, essential for a multichannels ASIC. Residual dispersion of 0.05~\%,
+0.013~\% and 0.012~\% have respectively been obtained for gain 8, 4 and
+2.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img48.eps}
+\caption{Gain uniformity for $G_{pa}=8, 4, 2$.}
+\label{fig:38}
+\end{figure}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{DAC linearity}
+\label{ssec:DAClinearity}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The DAC linearity has been measured and it consists in measuring the
+voltage DAC ($V_{dac}$) amplitude obtained for different DAC register
+values. \refFig{fig:39} gives the evolution of $V_{dac}$ as a function of the register for the two
+DACs and residuals from $-0.1~\%$ to $0.1~\%$.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img49.eps}
+%\includegraphics{img50.eps}
+\caption{DAC linearity; DAC1 and DAC2 respectively.}
+\label{fig:39}
+\end{figure}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Trigger output}
+\label{ssec:TriggerMeas}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The trigger output behavior was studied scanning the threshold for
+different injected charges. At first no charge was injected which
+corresponds to measure the fast shaper pedestal. The result is
+represented on \refFig{fig:40}  for each channel. The  S-curves 
+are superimposed meaning good homogeneity. The spread
+is of one DAC count ($LSB DAC = 1.78$~mV) or 0.06~pe.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img51.eps}
+\caption{Pedestal S-curves for channel 1 to 16.}
+\label{fig:40}
+\end{figure}
+
+The trigger efficiency was then measured for a
+fixed injected charge of 10~pe. On \refFig{fig:41} are represented the S-curves
+obtained with 200 measurements of the trigger for all channels varying
+the threshold. The homogeneity is proved by a spread of 7 DAC unit (0.4~pe) and a noise of 0.07 pe ($RMS =2.19$).
+
+\begin{figure}[hbtp]
+%\includegraphics{img52.eps}
+%\includegraphics{img53.eps}
+%\includegraphics{img54.eps}
+\caption{Fast shaper and trigger (top panel); S-curves for input of 10~pe (left panel);
+uniformity plot for channel 1 to 16 (right panel).}
+\label{fig:41}
+\end{figure}
+
+The trigger output is studied also by scanning
+the threshold for a fixed channel and changing the injected charge. On \refFig{fig:42}
+on the left panel  is shown the trigger efficiency versus the DAC unit and on
+the right panel is plotted the threshold versus the injected charge but only
+until 0.5~pC. From these measurements a noise of 10~fC has been
+extrapolated. Therefore the threshold is only possible above $10~\sigma$ of the noise due to the discriminator coupling
+(\refFig{fig:43}).
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img55.eps}
+%\includegraphics{img56.eps}
+\caption{Trigger efficiency vs DAC count up to 300~pe (left panel) and
+until 3~pe (right panel).}
+\label{fig:42}
+\end{figure}
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img57.eps}
+\caption{Threshold vs injected charge up to 500~fC. It is shown the 1~p.e threshold for a PMT gain of $10^6$.}
+\label{fig:43}
+\end{figure}
+
+The trigger coupling illustrated in \refFig{fig:44} with the
+injected charge in channel 1 and output signal observed in channel 2,
+shows a coupling signal around 25~mV (10~fC). This coupling signal is
+due, probably, to the input power supply ($V_{dd-pa}$ and $V_{ss}$).
+
+\begin{figure}[hbtp]
+%\includegraphics{img58.eps}
+\caption{Trigger coupling signal.}
+\label{fig:44}
+\end{figure}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{ADC characterisation}
+\label{ssec:ADCMeas}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The ADC performance has been studied alone and with the whole chain. Injecting to the
+ ADC input directly a DC voltage by the internal DAC,
+in order to have a voltage level as stable as possible, were measured
+the ADC values for all channels (\refFig{fig:45}).
+
+The measurement is repeated 10000 times for
+each channel and in the first plot of the LabView front panel window (\refFig{fig:45}). The
+minimal, maximal and mean values, over all acquisitions, for each
+channel are plotted. In the second plot there is the rms charge value
+versus channel number with a value in the range $[0.5, 1]$ ADC unit.
+Finally the third plot shows an example of charge amplitude
+distribution for a single channel: a spread of 5 ADC counts is
+obtained.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img59.eps}
+\caption{ADC measurements with DC input 1.45~V (middle scale).}
+\label{fig:45}
+\end{figure}
+
+The ADC is suited to a multichannel conversion
+so the uniformity and linearity are studied in order to characterize
+the ADC behaviour. On \refFig{fig:46} is represented the ADC transfer function for the
+10-bit ADC versus the input voltage level. All channels are represented
+and have plots superimposed. 
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img60.eps}
+\caption{10  bits ADC transfer function vs input charge.}
+\label{fig:46}
+\end{figure}
+
+The good homogeneity observed is confirmed by
+the linear fit parameters comparison. In  are plotted the slope and the
+intercept distributions for all channels. The RMS slope value of 0.143
+and the RMS intercept value of 0.3 confirm the 10-bits ADC uniformity
+(\refTab{tab:12}).
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img61.eps}
+%\includegraphics{img62.eps}
+\caption{Evolution of the fit parameters (slope on the
+left panel and intercept on the right panel) as a function of the channel
+number.}
+\label{fig:47}
+\end{figure}
+
+\begin{table}
+\centering
+\caption{TO BE COMPLETED. 10 bits ADC parameter fits.... 25 acquisitions per channel, $LSB = 1.06$~mV...}
+\label{tab:12}
+\begin{tabular}{|l|c|c|}
+\hline
+   & Slope      & Intercept \\
+Mean & 936.17   & 859.8 \\
+RMS  & 0.14     & 0.3   \\ 
+\hline
+\end{tabular}
+\end{table}
+
+In \refFig{fig:48} are shown respectively the 12, 10 and 8 bits ADC
+linearity plots with the 25 measurements made for each input voltage
+level. The average ADC count value is plotted versus the input signal.
+The residuals from $-1.5$ to $0.9$ ADC units for the 12-bits ADC; from $-0.5$
+to $0.4$ for the 10-bit ADC and from $-0.5$ to $0.5$ for the 8-bit ADC. This prove
+the good ADC behaviour in terms of Integral non linearity. 
+
+\begin{figure}[hbtp]
+%\includegraphics{img63.eps}
+%\includegraphics{img64.eps}
+%\includegraphics{img65.eps}
+\caption{12, 10, 8 bit ADC linearity.}
+\label{fig:48}
+\end{figure}
+In terms of Differential non linearity, the
+value from $-1.0$ to $0.65$ for the 10 bit ADC and from $-0.3$ to $0.2$ for the 8
+bit ADC, show us a good behaviour even if the plots are the results of
+preliminary measurements.
+
+\begin{figure}[htb]
+%\includegraphics{img66.eps}
+%\includegraphics{img67.eps}
+\caption{Differential non linearity.}
+\label{fig:49}
+\end{figure}
+
+Once the ADC performances have been tested
+separately, the measurements are performed on the complete chain. The
+results of the input signal autotriggered, held in the T\&H and
+converted in the ADC are illustrated in  where are plotted the 10-bit
+ADC counts in function of the variable input charge (up to 50~pe). A
+good linearity of $1.4~\%$ and a noise of 6 ADC units are obtained. In \refTab{tab:13}
+are listed the setting value for measurements.
+
+\begin{table}
+        \centering
+        \caption{TO BE COMPELTED. $G_{pa}=14$ ($C_{in}=7$~pF , $C_f=0.5$~pF),
+Slow shaper $RC=50$~ns,
+DAC delay: $bit<0> = 1$ \& $bit<2> = 1$.
+}
+        \label{tab:13}
+\begin{tabular}{|l|c|c|c|}
+\hline
+Parameters & 12 bits ADC & 10 bits ADC & 8 bits ADC\\
+\hline 
+LSB         & $0.27$ & $1.06$~mV  & $4.26$~mV\\
+Min ADC count at 3~pe& $509$ &  $132$ & $33$  \\
+Max ADC count at 50~pe & $3873$ &  $989$ & $241$ \\
+Residuals in ADC units &$[21,54]$ & $[6,14]$  & $[2,3]$ \\
+\hline
+\end{tabular}
+\end{table}
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img68.eps}
+\caption{10 bit ADC linearity.}
+\label{fig:50}
+\end{figure}
+
+On \refFig{fig:51} is plotted the 8-bit linearity at $1.4~\%$
+and a noise of 1.53 ADC unit. In \refTab{tab:13} are listed the setting value for
+measurements.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img69.eps}
+\caption{8 bit ADC linearity.}
+\label{fig:51}
+\end{figure}
+
+On  \refFig{fig:53} is plotted the 12-bit linearity
+at $1.4~\%$ and a noise of 23.69 ADC unit. In \refTab{tab:13} are listed the setting
+value for measurements.
+
+\begin{figure}[hbtp]
+%\includegraphics{img70.eps}
+\caption{12 bit ADC linearity.}
+\label{fig:52}
+\end{figure}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{Measurements with PMTs}
+\label{sec:MeasWithPMT}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The first measurements with a photomultiplier at input are started in
+IPNO at Orsay.
+
+\begin{figure}[hbtp]
+\centering
+%\includegraphics{img71.eps}
+\caption{TO BE COMPLETED}
+\label{fig:53}
+\end{figure}
+
 \acknowledgments
 %\begin{acknowledgments}
-
-We wish to warmly acknowledge support from all the various funding agencies.  We wish to thank the EU framework 6 project ILIAS for providing assistance particularly regarding underground site aspects (contract 8R113-CT-2004-506222).
-
+This work, especially one of the author, is supported by the National Reasaerch Agency under contract ANR-06-BLAN-0186.
 %\end{acknowledgments}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \newpage
-\section*{References}
+%\section*{References}
 \bibliography{campagne}
 \end{document}