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Selma/PARISROC/parisroc-jinst.tex
r468 r473 1 1 \documentclass{JINST} 2 %\usepackage{graphicx}3 2 \usepackage[pdftex]{graphicx} 4 3 \usepackage[figuresright]{rotating} 5 \usepackage[T1]{fontenc} 4 %\usepackage{graphicx} 5 %\usepackage[T1]{fontenc} 6 6 \usepackage{eurosym} 7 \usepackage{rotating} 7 %\usepackage{rotating} 8 %\usepackage[dvips]{color} 9 8 10 9 11 %used explicitly in the text … … 15 17 16 18 17 \title{ Large underground, liquid based detectors for astro-particle physics in Europe: scientific case and prospects}19 \title{PARISROC, a Photomultiplier Array Integrated Readout Chip.} 18 20 % 19 21 20 \author{ First Author$^a$, Second Author$^b$\thanks{Corresponding22 \author{S. Conforti$^a$, Second Author$^b$\thanks{Corresponding 21 23 author.}~ and Third Author$^b$\\ 22 \llap{$^a$} Name of Institute,\\23 Address, Country\\24 \llap{$^a$}Laboratoire de l'Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud 11, 25 Bât. 200, 91898 Orsay Cedex, France\\ 24 26 \llap{$^b$}Name of Institute,\\ 25 27 Address, Country\\ 26 E-mail: \email{ CorrespondingAuthor@email.com}}28 E-mail: \email{conforti@lal.in2p3.fr}} 27 29 28 30 … … 30 32 31 33 \abstract{ 32 33 This document reports on a series of experimental and theoretical studies conducted to 34 assess the astro-particle physics potential of three future large-scale particle detectors 35 proposed in Europe as next generation underground observatories. 36 34 PARISROC is a complete read 35 out chip, in AMS SiGe 0.35 \begin{math}\mu{}\end{math}m technology 36 \cite{ref1} 37 %[1] 38 , for photomultipliers array. It allows triggerless acquisition for 39 next generation neutrino experiments and it belongs to an R\&D program 40 funded by French national agency for research (ANR) called 41 PMm2: "`Innovative electronics for photodetectors array 42 used in High Energy Physics and Astroparticles"' 43 \cite{ref2} 44 %[2] 45 (ref.ANR-06-BLAN-0186). The ASIC integrates 16 independent and auto 46 triggered channels with variable gain and provides charge and time 47 measurement by a 12-bit ADC and a 24-bit Counter. The charge 48 measurement should be performed from 1 up to 300 pe with a good 49 linearity. The time measurement allowed to a coarse time with a 24-bit 50 counter at 10 MHz and a fine time on a 100ns ramp to achieve a 51 resolution of 1 ns. The ASIC sends out only the relevant data through 52 network cables to the central data storage. 37 53 }%end of abstract 38 54 … … 40 56 %97.60.Bw} 41 57 42 %\submitto{Journal of Cosmology and Astroparticle Physics}58 %\submitto{Journal of Instrumentation} 43 59 44 60 \keywords{Keyword1; Keyword2; Keyword3} … … 48 64 \bibliographystyle{Campagne} 49 65 50 \section{Physics motivation} 51 \label{sec:Phys-Intro} 52 53 Our last citation \cite{Genolini:2008uc}..... 54 55 The RMS error is $\sigma$... 56 57 58 Several outstanding physics goals could be achieved by the next generation of large underground observatories 59 in the domain of astro-particle and particle physics, neutrino astronomy and cosmology. 60 Proton decay \cite{Pati:1973rp}, in particular, is one of the most exciting prediction of Grand Unified Theories 61 (for a review see \cite{Nath:2006ut}) aiming at the 62 unification of fundamental forces in Nature. It remains today one of the most relevant open questions 63 of particle physics. Its discovery would certainly represent a fundamental milestone, contributing to clarifying our 64 understanding of the past and future evolution of the Universe. 65 66 \section{Introduction} 67 \label{sec:Intro} 68 69 The PMm2 project: "`Innovative electronics for 70 photodetectors array used in High Energy Physics and 71 Astroparticles"' \cite{ref2} 72 %[2] 73 proposes to segment the large surface of photodetection in macro 74 pixel consisting of an array of 16 photomultipliers connected to an 75 autonomous front-end electronics () and powered by a common High 76 Voltage. These large detectors are used in next generation proton decay 77 and neutrino experiment (i.e. the post-SuperKamiokande detectors as 78 those that will take place in megaton size water tanks) and will 79 require very large surfaces of photo detection and a large volume of 80 data. The micro-electronics group's (OMEGA from the LAL at Orsay) 81 purpose is the front-end electronics conception and 82 realization. This R\&D \cite{ref2} 83 %[2] 84 involves three French laboratories (LAL Orsay, LAPP Annecy, IPN 85 Orsay) and ULB Bruxells for the DAQ. It is funded for three years by 86 the French National Agency for Research (ANR) under the reference 87 ANR-06-BLAN-0186. 88 89 90 LAL Orsay is in charge of the design and tests of the readout chip 91 named PARISROC which stands for Photomultiplier ARrray Integrated in 92 Si-Ge Read Out Chip. 66 93 67 94 \begin{figure}[htb] 68 95 \begin{center} 69 \includegraphics[scale=0.5]{./test_figs/varvscycle.pdf} 96 \includegraphics[width=0.7\columnwidth]{img0.jpg} 97 \caption{Principal of PMm2 proposal for megaton scale Cerenkov water 98 tank.} 99 \label{fig:1} 70 100 \end{center} 71 \caption{Example of figure PDF} 72 \label{fig:1} 73 \end{figure} 74 75 76 77 101 \end{figure} 102 103 The detectors such as SuperKamiokande, are large tanks covered by a 104 significant number of large photomultipliers (20"), 105 the next generation neutrino experiments will require a bigger surface 106 of photo detection and thus more photomultipliers. As a consequence the 107 total cost has an important relief \cite{ref1}. 108 \begin{itemize} 109 \item A smaller number of electronics, thanks to the 16 PMTs macropixel with 110 a common electronics, even if it induces more electronic channels; 111 \item A common High Voltage for the 16 PMTs so a reduced number of 112 underwater cables, cables that are also used to brought the DATA to 113 the surface; 114 \item The front-end closed to the PMTs that allow a suppression of 115 underwater connector. 116 \end{itemize} 117 118 The general principle of PMm2 project is that the ASIC and a FPGA 119 manage the dialog between the PMTs and the surface controller (\refFig{fig:2}). 120 121 \begin{center} 78 122 \begin{figure}[htb] 123 %%\includegraphics[width=0.7\columnwidth]{img1.eps} 124 \caption{Principle of the PMm2 project.} 125 \label{fig:2} 126 \end{figure} 127 \end{center} 128 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 129 \section{PARISROC architecture} 130 \label{sec:PARISROCArchi} 131 The ASIC Parisroc is composed of 16 analogue channels managed by a 132 common digital part (\refFig{fig:3}). 133 79 134 \begin{center} 80 \includegraphics[scale=0.5]{./test_figs/pulse_snapshot.jpg} 135 \begin{figure}[hbtp] 136 %%\includegraphics[width=0.7\columnwidth]{img2.eps} 137 \caption{PARISROC global schematic.} 138 \label{fig:3} 139 \end{figure} 81 140 \end{center} 82 \caption{Example figure JPEG} 83 \label{fig:2} 84 \end{figure} 85 86 Several experiments have been built and conducted to search for proton decay but they only yielded lower limits to the proton lifetime. 87 The window between the predicted proton lifetime (in the simplest models typically below $10^{37} $ years) and that excluded 88 by experiments \cite{Kobayashi:2005pe} 89 ($O$($10^{33}$) years, depending on the channel) is within reach, 90 and the demand to fill the gap grows with the progress in other domains of particle physics, astro-particle physics and cosmology. 91 To some extent, also a negative result from next generation high-sensitivity experiments 92 would be relevant to rule-out some of the 93 theoretical models based on SU(5) and SO(10) gauge symmetry or to further constrain the range of allowed parameters. 94 Identifying unambiguously proton decay and measuring its lifetime would set a firm scale for any Unified Theory, narrowing 95 the phase space for possible models and their parameters. This will be a mandatory step to go forward 96 beyond the Standard Model of elementary particles and interactions. 97 98 Another important physics subject is the physics of 99 %natural (A. Mirizzi 15may07) 100 astrophysical 101 neutrinos, as those from supernovae, from the Sun and from the interaction of primary cosmic-rays with the Earth's atmosphere. Neutrinos are above all important messengers from stars. 102 Neutrino astronomy has a glorious although recent history, from the detection of solar neutrinos 103 \cite{Davis:1968cp,Hirata:1989zj,Anselmann:1992um,Abdurashitov:1994bc,Smy:2002rz,Aharmim:2005gt,Altmann:2005ix} 104 to the observation of neutrinos from supernova explosion, \cite{Hirata:1987hu,Bionta:1987qt,Alekseev:1988gp}, 105 acknowledged by the Nobel Prizes awarded to M. Koshiba and R. Davis. 106 These observations have given valuable information for a better understanding of the functioning 107 of stars and of the properties of neutrinos. However, much more information could be obtained if the energy spectra of 108 stellar neutrinos were known with higher accuracy. 109 Specific neutrino observations could give detailed information on the conditions of the production zone, 110 whether in the Sun or in a supernova. 111 A supernova explosion in our galaxy would be extremely important as the evolution mechanism of the collapsed star 112 is still a puzzle for astrophysics. 113 An even more fascinating challenge would be observing neutrinos from extragalactic supernovae, either from identified sources 114 or from a diffuse flux due to unidentified past supernova explosions. 115 116 Observing neutrinos produced in the atmosphere as cosmic-ray secondaries 117 \cite{Aglietta:1988be,Hirata:1988uy,Hirata:1992ku,Becker-Szendy:1992hq,Daum:1994bf,Allison:1999ms,Ashie:2005ik} 118 gave the first compelling evidence 119 for neutrino oscillation \cite{Fukuda:1998mi,Kajita:2006cy}, a process that unambiguously points to the existence of new physics. 120 While today the puzzle of missing atmospheric neutrinos can be considered solved, 121 there remain challenges related to the sub-dominant oscillation phenomena. In particular, precise measurements of 122 atmospheric neutrinos with high statistics and small systematic errors \cite{TabarellideFatis:2002ni} 123 would help in resolving ambiguities and degeneracies that hamper the interpretation 124 of other experiments, as those planned for future long baseline neutrino oscillation measurements. 125 126 Another example of outstanding open questions is that of the knowledge of the interior of the Earth. 127 It may look hard to believe, but we know much better what happens inside the Sun than inside our own planet. 128 There are very few messengers that can provide information, while a mere theory is not sufficient for building a credible model for the Earth. However, there is a new unexploited window to the Earth's interior, 129 by observing neutrinos produced in the radioactive decays of heavy elements in the matter. Until now, only the KamLAND 130 experiment \cite{Araki:2005qa} has been able to study these so-called geo-neutrinos opening the way to a completely new 131 field of research. The small event rate, however, does not allow to draw significant conclusions. 132 133 The fascinating physics phenomena outlined above, in addition to other important subjects that we will address in the following, 134 could be investigated by a new generation of multipurpose 135 experiments based on improved detection techniques. 136 The envisioned detectors must necessarily be very massive (and consequently large) 137 due to the smallness of the cross-sections and to the low rate of signal events, 138 and able to provide very low experimental background. 139 The required signal to noise ratio can only be achieved in underground laboratories suitably shielded against cosmic-rays 140 and environmental radioactivity. 141 We can identify three different and, to large extent, complementary technologies capable to meet the challenge, based 142 on large scale use of liquids for building large-size, volume-instrumented detectors 143 144 \begin{itemize} 145 \item Water Cherenkov. 146 As the cheapest available (active) target material, water is the only liquid that is realistic for extremely large detectors, 147 up to several hundreds or thousands of ktons; detectors have sufficiently good resolution in energy, 148 position and angle. The technology is well proven, as previously used for the IMB, Kamiokande and Super-Kamiokande 149 experiments. 150 151 \item Liquid scintillator. 152 Experiments using a liquid scintillator as active target 153 provide high-energy resolution and offer low-energy threshold. They are 154 particularly attractive for low energy particle detection, as for example solar 155 neutrinos and geo-neutrinos. Also liquid scintillator detectors feature a well established technology, 156 already successfully applied at relatively large scale to the Borexino 157 \cite{Back:2004zn} and KamLAND \cite{Araki:2004mb} experiments. 158 159 160 \item Liquid Argon Time Projection Chambers (LAr TPC). 161 This detection technology has among the three the best performance in identifying the topology of 162 interactions and decays of particles, thanks to the bubble-chamber-like imaging performance. 163 Liquid Argon TPCs are very versatile and work well with a wide particle energy range. 164 Experience on such detectors has been gained within the ICARUS project \cite{Amerio:2004ze,Arneodo:2001tx}. 165 \end{itemize} 166 167 Three experiments are proposed to employ the above detection techniques: MEMPHYS \cite{deBellefon:2006vq} for WC, 168 LENA \cite{Oberauer:2005kw, Marrodan:2006} for liquid scintillator 169 and GLACIER \cite{Rubbia:2004tz,Rubbia:2004yq,Ereditato:2004ru,Ereditato:2005ru,Ereditato:2005yx} for Liquid Argon. 170 In this paper we report on the study of the physics potential of the experiments and identify features of complementarity 171 amongst the three techniques. 172 173 Needless to say, the availability of future neutrino beams from particle accelerators 174 would provide an additional bonus to the above experiments. 175 Measuring oscillations with artificial neutrinos (of well known kinematical features) 176 with a sufficiently long baseline would allow to accurately determine the oscillation parameters 177 (in particular the mixing angle $\theta_{13}$ and the possible 178 CP violating phase in the mixing matrix). 179 The envisaged detectors may then be used for observing neutrinos from the future Beta Beams and Super Beams 180 in the optimal energy range for each experiment. A common example 181 %C Volpe 19/10/07 is a low-energy Beta Beam from CERN to MEMPHYS at Frejus, 130 km away 182 is a Beta Beam from CERN to MEMPHYS at Frejus, 130 km away \cite{Campagne:2006yx}. 183 High energy beams have been suggested \cite{Rubbia:2006pi}, 184 favoring longer baselines of up to $O$(2000~km). 185 %add C. Volpe review 186 An exhaustive review on the different Beta Beam scenario can be found in the reference \cite{Volpe:2006in}. 187 The ultimate Neutrino Factory facility will require a magnetized detector to fully exploit the simultaneous availability of 188 neutrinos and antineutrinos. This subject is however beyond the scope of the present study. 189 190 Finally, there is a possibility of (and the hope for) unexpected 191 discoveries. The history of physics has shown that 192 several experiments have made their glory with discoveries in research fields that were outside the original goals of the experiments. 193 Just to quote an example, we can mention the Kamiokande detector, mainly designed to search for proton decay 194 and actually contributing to the observation of atmospheric neutrino oscillations, to the clarification of the solar neutrino puzzle and 195 to the first observation of supernova neutrinos \cite{Hirata:1987hu,Hirata:1988ad,Hirata:1989zj,Hirata:1988uy, 196 Fukuda:1998mi}. 197 All the three proposed experiments, thanks to their 198 outstanding boost in mass and performance, will certainly provide a significant potential for surprises and unexpected discoveries. 199 200 % 141 142 Each analogue channel is made of a low noise preamplifier with 143 variable and adjustable gain. The variable gain is common for all 144 channels and it can change from 8 to 1 on 4 bits. The gain is also 145 tuneable channel by channel to adjust the input detector's gain, up to 146 a factor 4 to an accuracy of 7\% with 8 bits. 147 148 The preamplifier is followed by a slow channel for the charge 149 measurement in parallel with a fast channel for the trigger output. 150 151 The slow channel is made by a slow shaper followed by an analogue 152 memory with a depth of 2 to provide a linear charge measurement up to 153 50~pC; this charge is converted by a 12-bits Wilkinson ADC. One follower 154 OTA is added to deliver an analogue multiplexed charge measurement. 155 156 The fast channel consists in a fast shaper (15~ns) followed by 2 low 157 offset discriminators to auto-trig down to 50~fC. The thresholds are 158 loaded by 2 internal 10-bit DACs common for the 16 channels and an 159 individual 4bit DAC for one discriminator. The 2 discriminator outputs 160 are multiplexed to provide only 16 trigger outputs. Each output trigger 161 is latched to hold the state of the response until the end of the clock 162 cycle. It is also delayed to open the hold switch at the maximum of the 163 slow shaper. An "`OR"' of the 16 trigger gives a 17th output. 164 165 166 For each channel, a fine time measurement is made by an analogue 167 memory with depth of 2 which samples a 12-bit ramp, common for all 168 channels, at the same time of the charge. This time is then converted 169 by a 12 bit Wilkinson ADC. 170 171 The two ADC discriminators have a common ramp, of 8/10/12 bits, as 172 threshold to convert the charge and the fine time. In addition a bandgap bloc provides all voltage references. 173 174 \begin{center} 175 \begin{figure}[hbtp] 176 %%\includegraphics[width=0.7\columnwidth]{img3.eps} 177 \caption{PARISROC Layout.} 178 \label{fig:4} 179 \end{figure} 180 \end{center} 181 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 182 \subsection{Analogue Channel description and simulations} 183 \label{ssec:AnalogChannel} 184 %%%%%%%%%%%%%%%%%%%%%%%%%%% 185 \refFig{fig:5} represents, in a schematic way, the detail of one channel analogue 186 part. 187 188 \begin{center} 189 \begin{figure}[hbtp] 190 %%\includegraphics[width=0.7\columnwidth]{img4.eps} 191 \caption{PARISROC one channel analogue part schematic.} 192 \label{fig:5} 193 \end{figure} 194 \end{center} 195 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 196 \subsection{Preamplifier} 197 \label{ssec:Preamplifier} 198 %%%%%%%%%%%%%%%%%%%%%%%%%%% 199 The input preamplifier is a low noise preamplifier with variable gain 200 thanks to the switched input ($C_{in}$) and feedback ($C_f$) capacitors that 201 can be adjusted (\refFig{fig:6}). 202 203 This gain can vary changing $C_{in}$, which is 204 common to the 16 channels, over 4 bits and $C_{f}$, to adjust preamplifier 205 gain channel by channel. This adjustment allows correction of the PMT 206 gain dispersion due to a use of a common HV. 207 208 \begin{center} 209 \begin{figure}[htb] 210 %%\includegraphics[width=0.7\columnwidth]{img5.eps} 211 \caption{PARISROC preamplifier schematic.} 212 \label{fig:6} 213 \end{figure} 214 \end{center} 215 216 The preamplifier is designed as a voltage 217 preamplifier in p-type Cascode structure to allow the acquisition of a 218 fast input signal with a large dynamic range. 219 220 The input transistor is a PMOS in common source 221 configuration: $W = 800~\mu$m; $L = 0.35~\mu$m; the big input transistor is 222 chosen to keep the preamplifier noise contribution low and to achieve a 223 high gm. It supplies the output (the drain terminal) to the input 224 terminal (source terminal) of the second stage transistor: $W = 100~\mu$m; 225 $L = 0.35~\mu$m; the output transistor must be small to reach preamplifier 226 high speed performances. The utility of the cascode preamplifier is in 227 the large input impedance of the common source (with also the 228 characteristic of Current Buffer) and better frequency response of a 229 common Gate. An output buffer stage is designed in order to adapt the 230 output impedance to the loaded impedance. The input dc level is high 231 (about 2.6~V) while the output dc level is low (about 1~V). Because of 232 the single side structure of preamplifier, it is hard to use the 233 external reference voltage to set the dc operating point; the idea is 234 to use an OTA as the dc feedback amplifier. 235 236 In \refFig{fig:7} are shown preamplifier's output waveforms 237 for fixed gain and different input signal (left panel) and for fixed 238 input signal and different preamplifier gain (right panel). 239 240 \begin{center} 241 \begin{figure}[hbtp] 242 %%\includegraphics[width=0.7\columnwidth]{img6.eps}%%\includegraphics[width=0.7\columnwidth]{img7.eps} 243 \caption{Simulated preamplifier output waveforms for different input 244 signals with fixed gain (left panel) and for fixed input 245 signal at different gain (different input capacitor values (right 246 panel).} 247 \label{fig:7} 248 \end{figure} 249 \end{center} 250 251 The input signal, used in simulation, is a triangle signal with 4.5~ns 252 rise and fall time and 5~ns of duration as shown in \refFig{fig:8}. This current 253 signal is sent to an external resistor (50~Ohms) and varies from 0 to 5~mA 254 in order to simulate a PMT charge from 0 to 50~pC which represents 0 255 to 300 photo-electrons when the PM gain is $10^{6}$. 256 257 \begin{center} 258 \begin{figure}[hbtp] 259 %%\includegraphics[width=0.7\columnwidth]{img8.eps} 260 \caption{Simulation input signal.} 261 \label{fig:8} 262 \end{figure} 263 \end{center} 264 265 The \refFig{fig:9} displays the input dynamic range allowed to the preamplifier 266 linearity performance. \refTab{tab:1} lists the residuals obtained for different 267 gains and shows a good linearity (better than $\pm 1\%$). 268 269 \begin{center} 270 \begin{figure}[hbtp] 271 %%\includegraphics[width=0.7\columnwidth]{img9.eps} 272 \caption{Preamplifier linearity.} 273 \label{fig:9} 274 \end{figure} 275 \end{center} 276 277 278 \begin{table} 279 \centering 280 \caption{TO BE COMPLETED} 281 \label{tab:1} 282 \begin{tabular}{|c|c|c|c|} 283 \hline 284 $G_{pa}$ & $V_{out-max}$ & $Qi_{max}/n_{pe}$ & Residuals (\%) \\ 285 \hline 286 8 & 1.394~V & 40~pC/250~pe & -0.6 to 0.2 \\ 287 4 & 0.841~V & 48~pC/300~pe & -0.1 to 0.3 \\ 288 2 & 0.417~V & 48~pC/300~pe & -0.2 to 0.3 \\ 289 \hline 290 \end{tabular} 291 \end{table} 292 293 294 295 The \refFig{fig:10} displays the preamplifier noise with an 296 rms value of 13~fC and a Signal to Noise ratio of $\approx 12$. 297 \refTab{tab:2} summarizes the results obtained. 298 299 \begin{center} 300 \begin{figure}[hbtp] 301 \%%includegraphics{img10.eps} 302 \caption{Preamplifier noise simulation; $G_{pa}=8$; $C_{in}=4$~pF and 303 $C_{f}=0.5$~pF.} 304 \end{figure} 305 \label{fig:10} 306 \end{center} 307 308 \begin{table} 309 \centering 310 \caption{TO BE COMPLETED} 311 \label{tab:2} 312 \begin{tabular}{|c|c|c|} 313 \hline 314 RMS & SNR & $V_{out}(1 p.e)$ \\ 315 \hline 316 $468~\mu$V ($\approx 1/12$~p.e, $\approx 13$~fC ) & 11.6 & 5.43~mV\\ 317 \hline 318 \end{tabular} 319 \end{table} 320 321 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 322 \subsection{Trigger output} 323 \label{ssec:Trigger} 324 %%%%%%%%%%%%%%%%%%%%%%%%%%% 325 The PARISROC is a self-triggered device. The fast channel has been 326 conceived for this purpose.The amplified signal flows in a fast shaper that is a CRRC filter with 327 a time constant of 15~ns. Its high gain allows to send high signal to 328 the discriminator and thus to trigger easily on 1/3 of photo-electron. 329 It has a classical design: differential pair is followed by a buffer. 330 331 \begin{figure}[hbtp] 332 \centering 333 %%\includegraphics[width=0.7\columnwidth]{img11.eps} 334 \caption{Fast shaper schematics.} 335 \label{fig:11} 336 \end{figure} 337 338 The \refFig{fig:12} represents the fast shaper output 339 waveforms for a variable input signal. The \refTab{tab:3} lists the fast 340 shaper principal characteristics obtained in simulation. 341 342 \begin{figure}[hbtp] 343 \centering 344 %%\includegraphics[width=0.7\columnwidth]{img12.eps} 345 %%\includegraphics[width=0.7\columnwidth]{img13.eps} 346 \caption{Simulated fast shaper outputs ($G_{pa} = 8$ with input from 1-10~pe (left panel) 347 and from 1/3~pe to 2~pe (right panel).} 348 \label{fig:12} 349 \end{figure} 350 351 \begin{table} 352 \centering 353 \caption{To be completed} 354 \label{tab:3} 355 \begin{tabular}{|c|c|c|c|} 356 \hline 357 RMS & SNR & $V_{out}(1 p.e)$ & $T_p$ \\ 358 \hline 359 $2.36~\mu$V ($\approx 1/16$~p.e, $\approx 10$~fC ) & 16 & 37.85~mV & 8~ns\\ 360 \hline 361 \end{tabular} 362 \end{table} 363 364 The fast shaper (15~ns) is followed by a low 365 offset discriminator to auto-trig down to 50~fC (1/3~pe at $10^6$ gain). 366 367 368 The two discriminators can be used alone or 369 simultaneously. Their outputs are multiplexed to ease the choice. Both 370 are simple low offset comparators with the same schematic. The 371 difference comes from the way to set the threshold. The first 372 discriminator has the threshold sets by one 10-bit DAC, common to all 373 16 channels, and one 4-bit DAC for each channel. The second 374 discriminator has the threshold sets by only the 10 bit common DAC. 375 Each output trigger is latched to hold the state of the response in SCA 376 channel. In \refFig{fig:13} are shown the triggers and the zoom of the triggers rise 377 time in order to see the time walk of around 4~ns. 378 379 380 \begin{figure}[hbtp] 381 \centering 382 %%\includegraphics[width=0.7\columnwidth]{img14.eps} 383 %%\includegraphics[width=0.7\columnwidth]{img15.eps} 384 \caption{Simulated trigger output (input charge from 0 to 10~p.e; 385 threshold at 1/3~p.e). Zoom of trigger rise time on right 386 pannel.} 387 \label{fig:13} 388 \end{figure} 389 390 Each output trigger is latched to hold the 391 state of the response in SCA channel. SCA channel is the also called 392 "`Analogue memory"'. The SCA has a 393 depth equal to two; this means that there are two T\&H for time 394 measurement as well as for charge measurement. 395 396 \begin{figure}[hbtp] 397 \centering 398 %%\includegraphics[width=0.7\columnwidth]{img16.eps} 399 \caption{SCA (switched capacitor array) scheme.} 400 \label{fig:14} 401 \end{figure} 402 403 The voltage level of the signal coming from 404 slow shaper or ramp TDC cell is memorised in the T\&H capacitor (500~fF) 405 so "`Track \& Hold Cell"' allows 406 to lock the capacitor value only when a calibrated trigger (from fast 407 channel) occurs within the selected column. The SCA column is selected, read and erased by 408 the digital part. 409 410 \begin{figure}[hbtp] 411 \centering 412 %%\includegraphics[width=0.7\columnwidth]{img17.eps} 413 \caption{Operation of T\&H cell.} 414 \label{fig:15} 415 \end{figure} 416 417 On \refFig{fig:15} is illustrated the T\&H cell mode of 418 operation: when a signal arrives in the discriminator cell is detected 419 and the output trigger signal is sent to the T\&H cell. 420 The output trigger is delayed and calibrated before being sent. 421 422 423 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 424 \subsection{Charge channel} 425 \label{ssec:Charge} 426 %%%%%%%%%%%%%%%%%%%%%%%%%%% 427 The charge channel is the slow channel: the signal amplified by the 428 variable gain preamplifier is sent to the slow shaper, a typical 429 $\mathrm{CRRC}^2$ filter with variable peaking time. The 430 peaking time can be set from 50~ns (default value) to 200~ns thanks to 431 the switched feedback capacitors. 432 433 On left part of \refFig{fig:16} are represented the slow shaper waveforms for 434 different shaping times and the same input signal. The noise value (\refTab{tab:4} 435 and right part of \refFig{fig:16}), from $980~\mu$V to $1.6$~mV (simulation results), foresee 436 good noise performance. 437 438 \begin{figure}[hbtp] 439 \centering 440 %%\includegraphics[width=0.7\columnwidth]{img18.eps} 441 %%\includegraphics[width=0.7\columnwidth]{img19.eps} 442 \caption{Slow shaper output waveforms simulation (left panel). Slow shaper 443 output noise simulation (right panel).} 444 \label{fig:16} 445 \end{figure} 446 447 \begin{table} 448 \centering 449 \caption{TO BE COMPLETED. $G_{pa} = 8$} 450 \label{tab:4} 451 \begin{tabular}{|c|c|c|c|} 452 \hline 453 Time constant & RMS & SNR & $V_{out}(1 p.e)$ \\ 454 \hline 455 50~ns & \parbox[t]{20mm}{$1.68$~mV \\ $\approx 1/17$~p.e \\ $ \approx 9$~fC} 456 & 11 457 & \parbox[t]{20mm}{$29$~mV \\ $T_p = 48$~ns } \\ 458 100~ns & \parbox[t]{20mm}{$1.26$~mV\\$\approx 1/12$~p.e \\ $ \approx 20$~fC} 459 & 8 460 & \parbox[t]{20mm}{$15$~mV \\ $T_p = 78$~ns }\\ 461 200~ns & \parbox[t]{20mm}{$0.98$~mV\\$\approx 1/5$~p.e \\ $ \approx 32$~fC} 462 & 5 463 & \parbox[t]{23mm}{$8$~mV \\ $ T_p = 141.5$~ns } \\ 464 \hline 465 \end{tabular} 466 \end{table} 467 468 The \refFig{fig:17} and \refTab{tab:5} illustrate the linearity performance for 469 different time constants. Simulations show a good linearity with 470 residuals from -0.5\% to 0.2\% at $T_p = 50$~ns, from 471 -1\% to 0.3\% at $T_p =100$~ns and -0.7\% to 0.3\% at 472 $T_p=200$~ns. 473 474 \begin{figure}[hbtp] 475 \centering 476 %%\includegraphics[width=0.7\columnwidth][width=273pt]{img20.eps} 477 \caption{Slow shaper linearity simulation.} 478 \label{fig:17} 479 \end{figure} 480 481 \begin{table} 482 \centering 483 \caption{TO BE COMPLETED} 484 \label{tab:5} 485 \begin{tabular}{|c|c|c|c|} 486 \hline 487 Time constante & $V_{out-max}$ & $Qi_{max}/n_{pe}$ & Residuals (\%) \\ 488 \hline 489 50~ns & 1.437~V & 13~pC/80~pe & -0.5 to 0.2 \\ 490 100~ns & 1.493~V & 24~pC/150~pe & -1.0 to 0.3 \\ 491 200~ns & 1.385~V & 48~pC/300~pe & -0.7 to 0.3 \\ 492 \hline 493 \end{tabular} 494 \end{table} 495 496 The Slow shaper maximum value, therefore the charge value, is then 497 memorized in the analogue memory, with a depth of 2, thanks to the 498 delayed trigger. \refFig{fig:18} gives the simulated slow shaper and SCA 499 signals. 500 501 \begin{figure}[hbtp] 502 \centering 503 %%\includegraphics[width=0.7\columnwidth][width=207pt]{img21.eps} 504 \caption{Slow shaper \& SCA simulation.} 505 \label{fig:18} 506 \end{figure} 507 This charge, stored as a voltage value, is then converted in digital 508 value thanks to the 8/10/12 bit Wilkinson ADC. 509 510 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 511 \subsection{Time measurement} 512 \label{ssec:Timemeas} 513 %%%%%%%%%%%%%%%%%%%%%%%%%%% 514 For each channel, a fine time measurement is performed by the analogue 515 memory with a depth of 2 which samples a 12 bit ramp (100~ns), common 516 for all channels, at the same time of the charge. 517 518 In \refFig{fig:19} is represented the TDC Ramp general schematic. The current, 519 which flows in feedback, charges the capacitance $C_f$ when the switch is 520 off. When the switch is turned off, $C_f$ discharges. Signals \verb|start\_ramp| and 521 \verb|start\_ramp\_b| manage the switches. The rising signal starts the ramp 522 and the falling signal stop the ramp (\refFig{fig:19}). 523 524 \begin{figure}[hbtp] 525 \centering 526 %%\includegraphics[width=0.7\columnwidth]{img22.eps} 527 %%\includegraphics[width=0.7\columnwidth]{img23.eps} 528 \caption{TDC Ramp general schematic.} 529 \label{fig:19} 530 \end{figure} 531 In order to avoid the large falling time of the ramp due to the $C_f$ 532 discharge time and the problem of non linearity at the start and the 533 end of ramp signal (\refFig{fig:20}), the real ramp is created from two 534 ramps. 535 536 \begin{figure}[hbtp] 537 \centering 538 %%\includegraphics[width=0.7\columnwidth]{img24.eps} 539 \caption{TDC Ramp.} 540 \label{fig:20} 541 \end{figure} 542 543 The signal start ramp, coming from the digital 544 part, enters in two delay cells. The two delayed signals create the 545 first and second ramps. Commutating alternatively two switches the 100~ns ramp TDC is created 546 (\refFig{fig:21} and \refFig{fig:22}). 547 548 \begin{figure}[hbtp] 549 \centering 550 %\includegraphics[width=0.7\columnwidth]{img25.eps} 551 \caption{TDC Ramp scheme.} 552 \label{fig:21} 553 \end{figure} 554 555 \begin{figure}[hbtp] 556 \centering 557 %\includegraphics[width=0.7\columnwidth]{img26.eps} 558 \caption{TDC Ramp simulation.} 559 \label{fig:22} 560 \end{figure} 561 562 This time value, stored as a voltage value, is then converted in 563 digital value tanks to the 8/10/12 bit Wilkinson ADC. 564 565 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 566 \subsection{ADC ramp} 567 \label{ssec:ADCramp} 568 %%%%%%%%%%%%%%%%%%%%%%%%%%% 569 In \refFig{fig:23} is represented the Ramp ADC general scheme. It is the 570 same as TDC ramp one, the difference is in a variable current source 571 which allows obtaining 8bit/10bit/12bit ADC according to the injected 572 current. \refTab{tab:6} gives, for each ramp, the time duration to reach 3.3~V. 573 574 \begin{figure}[hbtp] 575 \centering 576 %\includegraphics{img27.eps} 577 \caption{ADC ramp schematic.} 578 \label{fig:23} 579 \end{figure} 580 581 \begin{table} 582 \centering 583 \caption{TO BE COMPLETED} 584 \label{tab:6} 585 \begin{tabular}{|l|l|} 586 \hline 587 Header 1 & Header 2 \\ 588 12 bit ADC & From 0.9~V to 3.3~V in $102.0~\mu{}$s \\ 589 10 bit ADC & From 0.9~V to 3.3~V in $25.6~\mu{}$s \\ 590 \phantom{ }8 bit ADC & From 0.9~V to 3.3~V in $6.4~\mu{}$s \\ 591 \hline 592 \end{tabular} 593 \end{table} 594 595 Then the ADC ramp is compared thanks to a Discriminator to the voltage 596 values, which corresponds to charge and fine time values, stored in the 597 SCA. The digital converted DATA are then treated by the digital part. 598 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 599 \subsection{Digital part} 600 \label{ssec:Digital} 601 %%%%%%%%%%%%%%%%%%%%%%%%%%% 602 The digital part of PARISROC is built around 4 modules which are "`acquisition"', "`conversion"', "`readout"' and "`top manager"'. Actually, PARISROC is based on 2 memories. During acquisition, 603 discriminated analog signals are stored into an analog memory (the SCA: 604 switched capacitor array). The analog to digital conversion module 605 converts analog charges and times from SCA into 12 bits digital values. 606 These digital values are saved into registers (RAM). At the end of the 607 cycle, the RAM is readout by an external system. The block diagram is 608 given on \refFig{fig:24}. 609 610 611 \begin{figure}[hbtp] 612 \centering 613 %\includegraphics{img28.eps} 614 \caption{Block diagram of the digital part.} 615 \label{fig:24} 616 \end{figure} 617 618 This sequence is made thanks to the top manager module which controls 619 the 3 other ones. When 1 or more channels are hit, it starts ADC 620 conversion and then the readout of digitized data. The maximum cycle 621 length is about $200~\mu$s. During 622 conversion and readout, acquisition is never stopped. It means that 623 discriminated analog signals can be stored in the SCA at any time of 624 the sequence shown in on \refFig{fig:25}. 625 626 \begin{figure}[hbtp] 627 \centering 628 %\includegraphics{img29.eps} 629 \caption{Top manager sequence.} 630 \label{fig:25} 631 \end{figure} 632 633 The first module in the sequence is the acquisition 634 which is dedicated to charge and fine time measurements. It manages the 635 SCA where charge and fine time are stored as a voltage like. It also 636 integrates the coarse time measurement thanks to a 24-bit gray counter 637 with a resolution of 100~ns. Each channel has a depth of 2 for the SCA 638 and they are managed individually. Besides, SCA is treated like a FIFO 639 memory: analog voltage can be written, read and erased from this 640 memory. 641 642 643 \begin{figure}[hbtp] 644 \centering 645 %\includegraphics{img30.eps} 646 \caption{SCA analogue voltage} 647 \label{fig:26} 648 \end{figure} 649 650 Then, the conversion module converts analog values stored in 651 the SCA (charge and fine time: cf. \`refFig{fig:26}) in digital ones thanks to a 12-bit 652 Wilkinson ADC. The counter clock frequency is 40~MHz, it implies a 653 maximum ADC conversion time of $103~\mu$s 654 when it overflows. This module makes 32 conversions in 1 run (16 655 charges and 16 fine times). 656 657 Finally, the readout module permits to empty all the registers 658 to an external system. As it will only transfer hit channels, this 659 module will tag each frame with its channel number: it works as a 660 selective readout. The pattern used is composed of 4 data: 4-bit 661 channel number, 24-bit coarse time, 12-bit charge and 12-bit fine time. 662 The total length of one frame is 52 bits. The maximum readout time 663 appears when all channels are hit. About 832 bits of data are 664 transferred to the concentrator with a 10~MHz clock: the readout takes 665 about $100~\mu$s with $1~\mu$s between 2 frames. 666 667 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 668 \section{ASIC Laboratory tests} 669 \label{sec:ASICLAbTest} 670 %%%%%%%%%%%%%%%%%%%%%%%%%%% 671 The PARISROC has been submitted in June 2008; a first batch of 6 ASICs 672 has been produced and received in January 2009 (a second batch of 14 673 ASICs in May 2009. 674 675 The ASIC test has been a critical step in the PARISROC planning due to 676 the ASIC complexity.A dedicated test board has been designed and realized for this purpose 677 (\refFig{fig:27}). Its role is to allow the characterization of the chip and the 678 communication between photomultipliers and ASIC. This is possible 679 thanks to a dedicated Labview program that allows sending the ASIC 680 configuration (slow control parameters; ASIC parameters, etc) and 681 receiving the output bits via a USB cable connected to the test board. 682 The Labview is developed by LAL. 683 684 \begin{figure}[h] 685 \centering 686 %\includegraphics{img31.eps} 687 \caption{Test Board.} 688 \label{fig:27} 689 \end{figure} 690 691 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 692 \subsection{General tests} 693 \label{ssec:GeneralTest} 694 %%%%%%%%%%%%%%%%%%%%%%%%%%% 695 On \refFig{fig:28} is shown the Test Bench used in laboratory. It is composed by a 696 test board, a signal generator, an oscilloscope, multimeters and PC to 697 run labview program. 698 699 \begin{figure}[hbtp] 700 \centering 701 %\includegraphics{img32.eps} 702 \caption{Test Bench.} 703 \label{fig:28} 704 \end{figure} 705 706 The signal generator is a TEKTRONIX single 707 channel function generator. It is used to create the input charge 708 injected in the ASIC. The signal injected has the shaping as similar as 709 possible to the PMT signal. On \refFig{fig:28} is represented the generator input 710 signal and its characteristics. 711 712 \begin{figure}[hbtp] 713 \centering 714 %\includegraphics{img33.eps} 715 %\includegraphics{img34.eps} 716 \caption{Input signals} 717 \label{fig:29} 718 \end{figure} 719 720 At the beginning all the standard electrical 721 characteristics have been tested: DC levels, analogue output signals, 722 the analogue part characteristics and then the pedestals, the DAC 723 linearity, S\-curves (trigger efficiency as a function of the injected 724 charge or the threshold), the ADC linearity. The first purpose is the 725 comparison between simulation results and test measurements; most of 726 them are in agreement with the ASIC characteristics, obtained in 727 simulation. 728 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 729 \subsection{Analogue tests} 730 \label{ssec:AnalogueTest} 731 %%%%%%%%%%%%%%%%%%%%%%%%%%% 732 The DC level characterization is the first step in ASIC 733 characterization; in particular the DC uniformity of the analogue part 734 DC level for the different channels has to be measured. 735 736 In \refFig{fig:30} are represented the preamplifier, slow 737 shaper and fast shaper DC uniformity plots. The DC uniformity test has a small dispersion 738 of 0.4\%, 0.1\% and 0.05\% respectively for the preamplifier, the slow 739 shaper and the fast shaper (\refTab{tab:7}). 740 741 \begin{figure}[hbtp] 742 \centering 743 %\includegraphics{img35.eps} 744 %\includegraphics{img36.eps} 745 %\includegraphics{img37.eps} 746 \caption{DC uniformity.} 747 \label{fig:30} 748 \end{figure} 749 750 \begin{table} 751 \centering 752 \caption{TO BE COMPLETED} 753 \label{tab:7} 754 \begin{tabular}{|l|c|c|c|} 755 \hline 756 DC level & RMS \\ 757 Preamplifier & 3.8~mV (0.40~\%) \\ 758 Slow shaper & 1.3~mV (0.10~\%) \\ 759 Fast shaper & 1.0~mV (0.05\%) \\ 760 \hline 761 \end{tabular} 762 \end{table} 763 764 The second step is the analogue part output signals: Injecting a 765 charge equivalent to 10~pe, and setting a preamplifier gain at 8, are 766 observed and compared with simulation results all the output waveforms. 767 768 There is a good agreement in preamplifier results ( \refFig{fig:31} and \refTab{tab:8}), the 769 amplitude has the same value while time rise value has a difference of 770 3~ns. This difference is due to the output buffer placed in the test 771 board. 772 773 \begin{figure}[hbtp] 774 \centering 775 %\includegraphics{img38.eps} 776 %\includegraphics{img39.eps} 777 \caption{Measurement and simulation of the preamplifier output for 778 an input charge of 10~pe.} 779 \label{fig:31} 780 \end{figure} 781 782 \begin{table} 783 \centering 784 \caption{TO BE COMPLETED. Preamplifier parameters.... $G_{pa} = 8$. WHY not same parameters 1~pe and 10~p.e} 785 \label{tab:8} 786 \begin{tabular}{|l|c|c|} 787 \hline 788 & Measurement & Simulation \\ 789 \hline 790 Maximum voltage (10~pe) & 50.00~mV & 50.83~mV \\ 791 Rise time (10~pe) & 7.78~ns & 4.79~ns \\ 792 RMS noise & 1~mV & 0.47~mV \\ 793 without USB cable & 0.66~mV & \\ 794 Noise in pe & 0.2 & 0.086 \\ 795 without USB cable & 0.132 & \\ 796 Maximum voltage (1~pe) & 5.00~mV & 5.43~mV \\ 797 SNR (1~pe ????) & 5 & 11.6 \\ 798 without USB cable & 7.5 & \\ 799 \hline 800 \end{tabular} 801 \end{table} 802 803 The slow shaper waveforms are shown in \refFig{fig:32} while \refTab{tab:9} 804 summarizes the results. The first differences appear: a different value 805 in amplitude for slow shaper signal and fast shaper signal that is 806 probably associate, also, to the Output Buffer. The second relevant 807 difference is in noise value, in particular in slow shaper noise 808 performance (\refTab{tab:9}). 809 810 \begin{figure}[hbtp] 811 \centering 812 %\includegraphics{img40.eps} 813 %\includegraphics{img41.eps} 814 \caption{Measurement and simulation of the slow shaper output for an 815 input charge of 10~pe.} 816 \label{fig:32} 817 \end{figure} 818 819 \begin{table} 820 \centering 821 \caption{TO BE COMPLETED. $G_{pa} = 8$ and $RC = 50$~ns.} 822 \label{tab:9} 823 \begin{tabular}{|l|c|c|} 824 \hline 825 & Measurement & Simulation \\ 826 \hline 827 Maximum Voltage (10~pe) & 117~mV & 290~mV \\ 828 Rise time (10~pe) & 18.0~ns & 19.1~ns \\ 829 RMS noise & 4.0~mV & 1.7~mV \\ 830 Noise in pe & 0.3 & 0.08 \\ 831 Maximum Voltage (1~pe) & 12~mV & 19~mV \\ 832 SNR & 3 & 11 \\ 833 \hline 834 \end{tabular} 835 \end{table} 836 837 The Fast shaper results are shown in \refFig{fig:33} 838 and \refTab{tab:10}. 839 \begin{figure}[htb] 840 \centering 841 %\includegraphics{img73.eps} 842 %\includegraphics{img72.eps} 843 \caption{Measurement and simulation of the fast shaper output for an 844 input charge of 1 pe.} 845 \label{fig:33} 846 \end{figure} 847 848 849 \begin{table} 850 \centering 851 \caption{TO BE COMPLETED. $G_{pa} = 8$.} 852 \label{tab:10} 853 \begin{tabular}{|l|c|c|} 854 \hline 855 & Measurement & Simulation \\ 856 \hline 857 RMS noise & 2.5~mV & 2.4~mV \\ 858 Noise in pe & 0.08 & 0.05 \\ 859 Maximum Voltage (1~pe) & 30~mV & 42~mV \\ 860 SNR & 12 & 18 \\ 861 \hline 862 \end{tabular} 863 \end{table} 864 Another important characteristic is the 865 linearity. The output voltage in function of the input injected charge 866 is plotted for the different analogue signals. \refFig{fig:34} gives few examples for 867 the preamplifier at different gains. \refTab{11} summarizes the fit 868 results of these linearities. Good linearity performances are shown by 869 residuals (better than $\pm 2~\%$) value but for a 870 smaller dynamic range than simulation. 871 872 \begin{figure}[hbtp] 873 \centering 874 %\includegraphics{img42.eps} 875 %\includegraphics{img43.eps} 876 %\includegraphics{img44.eps} 877 \caption{Preamplifier linearity for different gains.} 878 \label{fig:34} 879 \end{figure} 880 881 \begin{table} 882 \centering 883 \caption{TO BE COMPLETED} 884 \label{tab:11} 885 \begin{tabular}{|c|c|c|c|} 886 \hline 887 Preamplifier Gains & Maximum voltage & Charge/Nb of pe & Residuals \\ 888 \hline 889 8 & 0.52~V & 12~pC / 78~pe & -1.0~\% to 0.8~\% \\ 890 4 & 0.64~V & 32~pC / 198~pe & -1.0~\% to 1.0~\% \\ 891 2 & 0.51~V & 50~pC / 312~pe & -2.0~\% to 1.5~\% \\ 892 \hline 893 \end{tabular} 894 \end{table} 895 896 897 \refFig{fig:35} represents an example of slow shaper 898 linearity for a time constant of 50~ns and a preamplifier gain of 8 899 with residuals better than $pm 1~\%$. 900 901 \begin{figure}[hbtp] 902 \centering 903 %\includegraphics{img45.eps} 904 \caption{Slow shaper linearity; $RC =50$~ns and $G_{pa}=8$.} 905 \label{fig:35} 906 \end{figure} 907 908 \refFig{fig:36} gives an example of the fast shaper linearity until an injected 909 charge of 10~pe. Residuals better than $ \pm 2~\%$ 910 are obtained. 911 912 \begin{figure}[hbtp] 913 \centering 914 %\includegraphics{img46.eps} 915 \caption{Fast shaper linearity up to 10~pe.} 916 \label{fig:36} 917 \end{figure} 918 919 The preamplifier linearity in function of 920 variable feedback capacitor value with an input charge of 10~pe and 921 with residuals from $-2.5~\%$ to $1.4~\%$ is represented on \refFig{fig:37} . The gain 922 adjustment linearity is nice at 2~\% on 8 bits. 923 924 \begin{figure}[hbtp] 925 \centering 926 %\includegraphics{img47.eps} 927 \caption{Preamplifier linearity vs feedback capacitor value.} 928 \label{fig:37} 929 \end{figure} 930 931 On \refFig{fig:38} is given the gain uniformity. For the 932 different preamplifier gains is plotted the maximum voltage value for 933 all channels in order to investigate the homogeneity among the whole 934 chip, essential for a multichannels ASIC. Residual dispersion of 0.05~\%, 935 0.013~\% and 0.012~\% have respectively been obtained for gain 8, 4 and 936 2. 937 938 \begin{figure}[hbtp] 939 \centering 940 %\includegraphics{img48.eps} 941 \caption{Gain uniformity for $G_{pa}=8, 4, 2$.} 942 \label{fig:38} 943 \end{figure} 944 945 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 946 \subsection{DAC linearity} 947 \label{ssec:DAClinearity} 948 %%%%%%%%%%%%%%%%%%%%%%%%%%% 949 The DAC linearity has been measured and it consists in measuring the 950 voltage DAC ($V_{dac}$) amplitude obtained for different DAC register 951 values. \refFig{fig:39} gives the evolution of $V_{dac}$ as a function of the register for the two 952 DACs and residuals from $-0.1~\%$ to $0.1~\%$. 953 954 \begin{figure}[hbtp] 955 \centering 956 %\includegraphics{img49.eps} 957 %\includegraphics{img50.eps} 958 \caption{DAC linearity; DAC1 and DAC2 respectively.} 959 \label{fig:39} 960 \end{figure} 961 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 962 \subsection{Trigger output} 963 \label{ssec:TriggerMeas} 964 %%%%%%%%%%%%%%%%%%%%%%%%%%% 965 The trigger output behavior was studied scanning the threshold for 966 different injected charges. At first no charge was injected which 967 corresponds to measure the fast shaper pedestal. The result is 968 represented on \refFig{fig:40} for each channel. The S-curves 969 are superimposed meaning good homogeneity. The spread 970 is of one DAC count ($LSB DAC = 1.78$~mV) or 0.06~pe. 971 972 \begin{figure}[hbtp] 973 \centering 974 %\includegraphics{img51.eps} 975 \caption{Pedestal S-curves for channel 1 to 16.} 976 \label{fig:40} 977 \end{figure} 978 979 The trigger efficiency was then measured for a 980 fixed injected charge of 10~pe. On \refFig{fig:41} are represented the S-curves 981 obtained with 200 measurements of the trigger for all channels varying 982 the threshold. The homogeneity is proved by a spread of 7 DAC unit (0.4~pe) and a noise of 0.07 pe ($RMS =2.19$). 983 984 \begin{figure}[hbtp] 985 %\includegraphics{img52.eps} 986 %\includegraphics{img53.eps} 987 %\includegraphics{img54.eps} 988 \caption{Fast shaper and trigger (top panel); S-curves for input of 10~pe (left panel); 989 uniformity plot for channel 1 to 16 (right panel).} 990 \label{fig:41} 991 \end{figure} 992 993 The trigger output is studied also by scanning 994 the threshold for a fixed channel and changing the injected charge. On \refFig{fig:42} 995 on the left panel is shown the trigger efficiency versus the DAC unit and on 996 the right panel is plotted the threshold versus the injected charge but only 997 until 0.5~pC. From these measurements a noise of 10~fC has been 998 extrapolated. Therefore the threshold is only possible above $10~\sigma$ of the noise due to the discriminator coupling 999 (\refFig{fig:43}). 1000 1001 \begin{figure}[hbtp] 1002 \centering 1003 %\includegraphics{img55.eps} 1004 %\includegraphics{img56.eps} 1005 \caption{Trigger efficiency vs DAC count up to 300~pe (left panel) and 1006 until 3~pe (right panel).} 1007 \label{fig:42} 1008 \end{figure} 1009 1010 \begin{figure}[hbtp] 1011 \centering 1012 %\includegraphics{img57.eps} 1013 \caption{Threshold vs injected charge up to 500~fC. It is shown the 1~p.e threshold for a PMT gain of $10^6$.} 1014 \label{fig:43} 1015 \end{figure} 1016 1017 The trigger coupling illustrated in \refFig{fig:44} with the 1018 injected charge in channel 1 and output signal observed in channel 2, 1019 shows a coupling signal around 25~mV (10~fC). This coupling signal is 1020 due, probably, to the input power supply ($V_{dd-pa}$ and $V_{ss}$). 1021 1022 \begin{figure}[hbtp] 1023 %\includegraphics{img58.eps} 1024 \caption{Trigger coupling signal.} 1025 \label{fig:44} 1026 \end{figure} 1027 1028 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 1029 \subsection{ADC characterisation} 1030 \label{ssec:ADCMeas} 1031 %%%%%%%%%%%%%%%%%%%%%%%%%%% 1032 The ADC performance has been studied alone and with the whole chain. Injecting to the 1033 ADC input directly a DC voltage by the internal DAC, 1034 in order to have a voltage level as stable as possible, were measured 1035 the ADC values for all channels (\refFig{fig:45}). 1036 1037 The measurement is repeated 10000 times for 1038 each channel and in the first plot of the LabView front panel window (\refFig{fig:45}). The 1039 minimal, maximal and mean values, over all acquisitions, for each 1040 channel are plotted. In the second plot there is the rms charge value 1041 versus channel number with a value in the range $[0.5, 1]$ ADC unit. 1042 Finally the third plot shows an example of charge amplitude 1043 distribution for a single channel: a spread of 5 ADC counts is 1044 obtained. 1045 1046 \begin{figure}[hbtp] 1047 \centering 1048 %\includegraphics{img59.eps} 1049 \caption{ADC measurements with DC input 1.45~V (middle scale).} 1050 \label{fig:45} 1051 \end{figure} 1052 1053 The ADC is suited to a multichannel conversion 1054 so the uniformity and linearity are studied in order to characterize 1055 the ADC behaviour. On \refFig{fig:46} is represented the ADC transfer function for the 1056 10-bit ADC versus the input voltage level. All channels are represented 1057 and have plots superimposed. 1058 1059 \begin{figure}[hbtp] 1060 \centering 1061 %\includegraphics{img60.eps} 1062 \caption{10 bits ADC transfer function vs input charge.} 1063 \label{fig:46} 1064 \end{figure} 1065 1066 The good homogeneity observed is confirmed by 1067 the linear fit parameters comparison. In are plotted the slope and the 1068 intercept distributions for all channels. The RMS slope value of 0.143 1069 and the RMS intercept value of 0.3 confirm the 10-bits ADC uniformity 1070 (\refTab{tab:12}). 1071 1072 \begin{figure}[hbtp] 1073 \centering 1074 %\includegraphics{img61.eps} 1075 %\includegraphics{img62.eps} 1076 \caption{Evolution of the fit parameters (slope on the 1077 left panel and intercept on the right panel) as a function of the channel 1078 number.} 1079 \label{fig:47} 1080 \end{figure} 1081 1082 \begin{table} 1083 \centering 1084 \caption{TO BE COMPLETED. 10 bits ADC parameter fits.... 25 acquisitions per channel, $LSB = 1.06$~mV...} 1085 \label{tab:12} 1086 \begin{tabular}{|l|c|c|} 1087 \hline 1088 & Slope & Intercept \\ 1089 Mean & 936.17 & 859.8 \\ 1090 RMS & 0.14 & 0.3 \\ 1091 \hline 1092 \end{tabular} 1093 \end{table} 1094 1095 In \refFig{fig:48} are shown respectively the 12, 10 and 8 bits ADC 1096 linearity plots with the 25 measurements made for each input voltage 1097 level. The average ADC count value is plotted versus the input signal. 1098 The residuals from $-1.5$ to $0.9$ ADC units for the 12-bits ADC; from $-0.5$ 1099 to $0.4$ for the 10-bit ADC and from $-0.5$ to $0.5$ for the 8-bit ADC. This prove 1100 the good ADC behaviour in terms of Integral non linearity. 1101 1102 \begin{figure}[hbtp] 1103 %\includegraphics{img63.eps} 1104 %\includegraphics{img64.eps} 1105 %\includegraphics{img65.eps} 1106 \caption{12, 10, 8 bit ADC linearity.} 1107 \label{fig:48} 1108 \end{figure} 1109 In terms of Differential non linearity, the 1110 value from $-1.0$ to $0.65$ for the 10 bit ADC and from $-0.3$ to $0.2$ for the 8 1111 bit ADC, show us a good behaviour even if the plots are the results of 1112 preliminary measurements. 1113 1114 \begin{figure}[htb] 1115 %\includegraphics{img66.eps} 1116 %\includegraphics{img67.eps} 1117 \caption{Differential non linearity.} 1118 \label{fig:49} 1119 \end{figure} 1120 1121 Once the ADC performances have been tested 1122 separately, the measurements are performed on the complete chain. The 1123 results of the input signal autotriggered, held in the T\&H and 1124 converted in the ADC are illustrated in where are plotted the 10-bit 1125 ADC counts in function of the variable input charge (up to 50~pe). A 1126 good linearity of $1.4~\%$ and a noise of 6 ADC units are obtained. In \refTab{tab:13} 1127 are listed the setting value for measurements. 1128 1129 \begin{table} 1130 \centering 1131 \caption{TO BE COMPELTED. $G_{pa}=14$ ($C_{in}=7$~pF , $C_f=0.5$~pF), 1132 Slow shaper $RC=50$~ns, 1133 DAC delay: $bit<0> = 1$ \& $bit<2> = 1$. 1134 } 1135 \label{tab:13} 1136 \begin{tabular}{|l|c|c|c|} 1137 \hline 1138 Parameters & 12 bits ADC & 10 bits ADC & 8 bits ADC\\ 1139 \hline 1140 LSB & $0.27$ & $1.06$~mV & $4.26$~mV\\ 1141 Min ADC count at 3~pe& $509$ & $132$ & $33$ \\ 1142 Max ADC count at 50~pe & $3873$ & $989$ & $241$ \\ 1143 Residuals in ADC units &$[21,54]$ & $[6,14]$ & $[2,3]$ \\ 1144 \hline 1145 \end{tabular} 1146 \end{table} 1147 1148 \begin{figure}[hbtp] 1149 \centering 1150 %\includegraphics{img68.eps} 1151 \caption{10 bit ADC linearity.} 1152 \label{fig:50} 1153 \end{figure} 1154 1155 On \refFig{fig:51} is plotted the 8-bit linearity at $1.4~\%$ 1156 and a noise of 1.53 ADC unit. In \refTab{tab:13} are listed the setting value for 1157 measurements. 1158 1159 \begin{figure}[hbtp] 1160 \centering 1161 %\includegraphics{img69.eps} 1162 \caption{8 bit ADC linearity.} 1163 \label{fig:51} 1164 \end{figure} 1165 1166 On \refFig{fig:53} is plotted the 12-bit linearity 1167 at $1.4~\%$ and a noise of 23.69 ADC unit. In \refTab{tab:13} are listed the setting 1168 value for measurements. 1169 1170 \begin{figure}[hbtp] 1171 %\includegraphics{img70.eps} 1172 \caption{12 bit ADC linearity.} 1173 \label{fig:52} 1174 \end{figure} 1175 1176 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 1177 \section{Measurements with PMTs} 1178 \label{sec:MeasWithPMT} 1179 %%%%%%%%%%%%%%%%%%%%%%%%%%% 1180 The first measurements with a photomultiplier at input are started in 1181 IPNO at Orsay. 1182 1183 \begin{figure}[hbtp] 1184 \centering 1185 %\includegraphics{img71.eps} 1186 \caption{TO BE COMPLETED} 1187 \label{fig:53} 1188 \end{figure} 1189 201 1190 \acknowledgments 202 1191 %\begin{acknowledgments} 203 204 We wish to warmly acknowledge support from all the various funding agencies. We wish to thank the EU framework 6 project ILIAS for providing assistance particularly regarding underground site aspects (contract 8R113-CT-2004-506222). 205 1192 This work, especially one of the author, is supported by the National Reasaerch Agency under contract ANR-06-BLAN-0186. 206 1193 %\end{acknowledgments} 1194 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 207 1195 \newpage 208 \section*{References}1196 %\section*{References} 209 1197 \bibliography{campagne} 210 1198 \end{document}
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